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PCA9421 Datasheet(PDF) 53 Page - NXP Semiconductors

Part # PCA9421
Description  Power management IC for low-power microcontroller applications
PDF  66 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9421 Datasheet(HTML) 53 Page - NXP Semiconductors

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NXP Semiconductors
PCA9421
Power management IC for low-power microcontroller applications
13.6 I2C Interface and Logic I/O
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SERIAL INTERFACE (SCL & SDA)
VPULLUP
Range[1]
Pullup Voltage Range
1.5
3.6
V
FI2C
I2C Clock frequency
On SCL
0
1000
kHz
VIH
HIGH-level Input voltage
1.5
V
VIL
LOW-level Input voltage
0.5
V
Vhys
Hysteresis of Schmitt
trigger inputs
0.01
V
VOL
LOW-level output voltage
at 3 mA sink current
0
0.4
V
VOL = 0.4 V; Standard and Fast
modes
3
mA
IOL
LOW-level output current
VOL = 0.6 V; Fast mode
6
mA
IIL
LOW-level input current
Pin voltage: 0.1xVpullup to 0.9x
Vpullup max
-10
10
µA
CI
Capacitance of IO pin
10
pF
tHD,STA
Hold time (repeated)
START condition
Fast mode plus; After this period,
the first clock pulse is generated
0.26
µs
tLOW
LOW period of I2C clock Fast mode plus
0.5
µs
tHIGH
HIGH period of I2C clock Fast mode plus
0.26
µs
tSU,STA
Setup time (repeated)
START condition
Fast mode plus
0.26
µs
tHD,DAT
Data Hold time
Fast mode plus
0
µs
tSU,DAT
Data Setup time
Fast mode plus
50
ns
tr
Rise time of I2C_SCL
and
I2C_SDA signals
Fast mode plus
120
ns
tf
Fall time of I2C_SCL and
I2C_SDA signals
Fast mode plus
120
ns
tSU,STO
Setup time for STOP
condition
Fast mode plus
0.26
µs
tBUF
Bus free time between
STOP and START
condition
Fast mode plus
0.5
µs
tVD,DAT
Data valid time
Fast mode plus
0.45
µs
tVD,ACK
Data valid acknowledge
time
Fast mode plus
0.45
µs
tSP
Pulse width of spikes that
must be suppressed by
input filter
0
50
ns
Table 67. EC table for I2C and Logic
PCA9421
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.0 — 16 October 2023
53 / 66



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