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PCA9421 Datasheet(PDF) 20 Page - NXP Semiconductors

Part # PCA9421
Description  Power management IC for low-power microcontroller applications
PDF  66 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9421 Datasheet(HTML) 20 Page - NXP Semiconductors

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NXP Semiconductors
PCA9421
Power management IC for low-power microcontroller applications
9.5 Register description
9.5.1 Device information (DEV_INFO, address 00h)
The device identification code stores a unique identifier for each version and/or revision of device, so that the
connected MCU recognizes it automatically.
This is a READ ONLY register.
Bit
Symbol
Default value Type
Function
7
DEV_ID [4]
0
R
6
DEV_ID [3]
0
R
5
DEV_ID [2]
0
R
4
DEV_ID [1]
0
R
3
DEV_ID [0]
0
R
Device ID
2
DEV_REV [2]
0
R
1
DEV_REV [1]
0
R
0
DEV_REV [0]
1
R
Device revision
Table 9. DEV_INFO register bit description
9.5.2 Top level interrupt status (TOP_INT, address 01h)
The top-level interrupt register contains flags indicating various top level interrupt events as indicated below.
An event is latched and only its first occurrence triggers the interrupt signal INTB (if it is not being masked).
Reoccurring events do not change the flag's status or trigger an additional interrupt. If multiple interrupt events
happen, its corresponding interrupt bits in the related registers are “triggered”, however, the INTB signal is only
triggered upon the first interrupt event.
The interrupt event reporting on the device is structured in a two-layer configuration. The interrupt events are
grouped as (1) system level; (2) buck regulator block; (3) LDO block. When any interrupt event is triggered,
based on which mode it falls into, the related bit for that mode in TOP_INT flags “1”. Any of the related bits in
TOP_INT only change back to 0 when all the interrupt events in its affiliated mode are cleared.
This is READ Only register.
Bit
Symbol
Default value
Type
Function
7
RSVD
0
R
Reserved bit
6
RSVD
0
R
Reserved bit
5
RSVD
0
R
Reserved bit
4
RSVD
0
R
Reserved bit
3
SYS_INT
0
R
System level interrupt event trigger indication from events reflected on
Sub level interrupt_0 register.
0: no system level interrupt event triggered
1: system level interrupt event triggered
2
VIN_INT
0
R
VIN_INT interrupt event trigger indication
0: no VIN_AUX_OK or VIN_ILIM interrupt event triggered
1: VIN_AUX_OK or VIN_ILIM interrupt event triggered
Table 10. TOP_INT register bit description
PCA9421
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.0 — 16 October 2023
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