SC68C198 datasheet(37/49 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC26C198 SC68C198

SC26L198 SC68L198

Octal UART with TTL compatibility at 3.3V

and 5V supply voltages

1995 May 1

372

A(7:0)

Read

Write

UART G

11100000 (xE0)

Mode Register g (MR2g)

11100001 (xE1)

Status Register g (SRg)

Command Register g (CRg)

11100010 (xE2)

Interrupt Status Register g (ISRg)

Interrupt Mask Register g (IMRg)

11100011 (xE3)

Receiver FIFO Reg g (RxFIFOg)

Transmitter FIFO Reg g (TxFIFOg)

11100100 (xE4)

Input Port Reg g (IPRg)

Reserved

11100101 (xE5)

I/O Port Interrupt and Output g (I/OPIORg)

11100110 (xE6)

Xon/XoffInterrupt Status Reg g (XISRg)

Reserved

11100111 (xE7)

Reserved

11101000 (xE8)

Reserved

11101001 (xE9)

Reserved

11101010 (xEA)

Reserved

11101011 (xEB)

Reserved

11101100 (xEC)

Reserved

11101101 (xED)

Reserved

11101110 (xEE)

Reserved

11101111 (xEF)

Reserved

UART H

11110000 (xF0)

Mode Register h (MR2h)

11110001 (xF1)

Status Register h (SRh)

Command Register h (CRh)

11110010 (xF2)

Interrupt Status Register h (ISRh)

Interrupt Mask Register h (IMRh)

11110011 (xF3)

Receiver FIFO Reg h (RxFIFOh)

Transmitter FIFO Reg h (TxFIFOh)

11110100 (xF4)

Input Port Reg h (IPRh)

Reserved

11110101 (xF5)

I/O Port Interrupt and Output h (I/OPIORh)

11110110 (xF6)

Xon/XoffInterrupt Status Reg h (XISRh)

Reserved

11110111 (xF7)

Reserved

11111000 (xF8)

Reserved

11111001 (xF9)

Reserved

11111010 (xFA)

Reserved

11111011 (xFB)

Reserved

11111100 (xFC)

Reserved

11111101 (xFD)

Reserved

11111110 (xFE)

Reserved

11111111 (xFF)

Reserved

RESET CONDITIONS

Device Configuration after Hardware Reset or CRa

cmd=x1F

Cleared registers:

Channel Status Registers (SR)

Channel Interrupt Status Registers (ISR)

Channel Interrupt Mask Registers (IMR)

Channel Interrupt Xon Status Register (XISR)

Interrupt Control Register (ICR)

Global Configuration Control Register (GCCR)

Hence the device enters the asynchronous bus cycling mode.

Current Interrupt Register (CIR)

BRG Timer Run Control Register (BRGTCR)

Watch-dog Timer Run Control Register (WDTRCR)

Channel Input/Output Port Configuration Registers (I/OPCR)

Hence all I/O pins have direction = Input after reset

BRG Counter/Timer Registers

Clears Modes for:

Power down

Test modes

Input Port Changed bits

Gang write to Xon or Xoff

Xon/Xoff/Address detection

Receiver error status

Disables:

Transmitters

Receivers

Interrupts, current and future

Halts:

BRG Counters

Bus cycle in progress (hardware RESET only)

SC68C198 Datasheet(PDF) 37 Page - NXP Semiconductors

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