UDA1321 datasheet(32/44 Pages) PHILIPS

32 / 44 page

1998 Oct 06

Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB)

Digital-to-Analog Converter (DAC)

UDA1321

SDA and SCL lines (standard I2C-bus); see Fig.7

fSCL

SCL clock frequency

−

100

kHz

tBUF

bus free time between a STOP

and START condition

4.7

−−

µs

tHD;STA

hold time (repeated) START

condition

4.0

−−

µs

tLOW

SCL LOW time

4.7

−−

µs

tHIGH

SCL HIGH time

4.0

−−

µs

tSU;STA

set-up time for a repeated START

condition

4.7

−−

µs

tSU;STO

set-up time for a STOP condition

4.0

−−

µs

tHD;DAT

data hold time

5.0

−

0.9

µs

tSU;DAT

data set-up time

250

−−

rise time of both SDA and SCL

signals

−−

1000

fall time of both SDA and SCL

signals

−−

300

CL(bus)

load capacitance for each bus line

−−

400

Oscillator; note 1

fosc

oscillator frequency

−

MHz

duty factor

−

transconductance

13.5

23.0

30.5

output resistance

450

700

1450

Ω

Ci(XTAL1)

parasitic input capacitance at XTAL1

Ci(XTAL2)

parasitic input capacitance at XTAL2

4.5

5.0

5.5

Istart

start current

4.3

8.8

15.0

Power-on reset

tsu(POR)

power-on reset set-up time

notes 2 and 3

5Cref

−−

Filter Stream DAC (FSDAC)

RES

resolution

−−

bits

Vo(FS)(rms)

full-scale output voltage

(RMS value)

VDD = 3.3 V

−

0.66

−

SVRR

supply voltage ripple rejection of

VDDA and VDDO

fripple = 1 kHz;

Vripple(p-p) = 0.1 V

−

∆V

o

channel unbalance

maximum volume

−

0.03

−

crosstalk between channels

RL =5kΩ−

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

UDA1321 Datasheet(PDF) 32 Page - NXP Semiconductors

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