STAC9750 datasheet(45/73 Pages) IDT

45 / 73 page

STAC9750/9751

VALUE-LINE TWO-CHANNEL AC’97 CODECS

PC AUDIO

IDT™

STAC9750/9751

V 5.8 103106

VALUE-LINE TWO-CHANNEL AC’97 CODECS

6.5.12.4.

SPSA1, SPSA0 (SPDIF Slot Assignment)

SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following

details the slot assignment relationship between SPSA1 and SPSA0.

The STAC9750/9751 are AMAP compliant with the following table.

6.5.13.

PCM DAC Rate Registers (2Ch and 32h)

The internal sample rate for the DACs and ADCs are controlled by the value in these read/write reg-

isters that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in

Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,

that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample

rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are

supported for record and playback. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h)

will read back with BB80h (48 KHz).

Table 25. Slot assignment relationship between SPSA1 and SPSA0

SPSA[1,0]

Slot Assignment

Comments

3 & 4

SPDIF source data slot assignment

7 & 8

2-channel CODEC primary default

6 & 9

4-channel CODEC primary default

10 & 11

6-channel CODEC primary default

Table 26. STAC9750/9751 AMAP compliant

CODEC

Function

SPSA = 00

SPSA = 01

SPSA = 10

SPSA = 11

2-channel Primary w/SPDIF

3 & 4

7 & 8*

6 & 9

10 & 11

2-channel Dock CODEC w/SPDIF

3 & 4

7 & 8

6 & 9*

10 & 11

+2-channel Surr w/ SPDIF

3 & 4

7 & 8

6 & 9*

10 & 11

+2-channel Cntr/LFE w/ SPDIF

3 & 4

7 & 8

6 & 9

10 & 11*

Note: * is the default slot assignment

Table 27. Hardware Supported Sample Rates

Sample Rate

SR15-SR0 Value

8 KHz

1F40h

11.025 KHz

2B11h

16 KHz

3E80h

22.05 KHz

5622h

32 KHz

7D00h

44.1 KHz

AC44h

48 KHz

BB80h

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