STAC9750 datasheet(16/73 Pages) IDT

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STAC9750/9751

VALUE-LINE TWO-CHANNEL AC’97 CODECS

PC AUDIO

IDT™

STAC9750/9751

V 5.8 103106

VALUE-LINE TWO-CHANNEL AC’97 CODECS

2.2.3.

Clocks

Figure 4. Clocks Timing

The STAC9750/9751 supports several clock frequency inputs as described in the following table. In

general, when a 24.576 MHz clock XTAL is not used, the XTAL_OUT pin should be tied to ground.

This short to ground configures the part into an alternate clock mode and enables an on board PLL.

Table 4. Clocks Specifications

Parameter

Symbol

Min

Typ

Max

Units

BIT_CLK frequency

12.288

MHz

BIT_CLK period

Tclk_period

81.4

BIT_CLK output jitter

750

BLT_CLK high pulse width (Note 1)

Tclk_high

40.7

BIT_CLK low pulse width (Note 1)

Tclk_low

40.7

SYNC frequency

48.0

KHz

SYNC period

Tsync_period

20.8

µs

SYNC high pulse width

Tsync_high

1.3

µs

SYNC low pulse width

Tsync_low

19.5

µs

Note:

Worst case duty cycle restricted to 45/55.

Table 5. Clock Mode Configuration

XTL_OUT

Pin Config

CID1

Pin Config

CID0

Pin Config

Clock Source Input

CODEC

Mode

CODEC

XTAL

float

24.576 MHz XTAL

XTAL or open

float

pulldown

12.288 MHz BIT_CLK

XTAL or open

pulldown

float

12.288 MHz BIT_CLK

XTAL or open

pulldown

12.288 MHz BIT_CLK

short to ground

float

14.31818 MHz source

short to ground

float

pulldown

27 MHz source

short to ground

pulldown

float

48 MHz source

short to ground

pulldown

24.576 MHz source

SYNC

BIT_CLK

Tclk_high

Tclk_low

Tclk_period

Tsync_high

Tclk_period

Tsync_low

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