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PM5352 Datasheet(PDF) 25 Page - PMC-Sierra, Inc |
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PM5352 Datasheet(HTML) 25 Page - PMC-Sierra, Inc |
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25 / 77 page ![]() PM5352 S/UNI STAR DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21 Pin Name Type Pin No. Function STPA Output (POS) B19 POS-PHY Selected multi-PHY Transmit Packet Available (STPA) signal. STPA transitions high when a predefined (TPAHWM[7:0] register bits) minimum number of bytes is available in the selected transmit FIFO (the FIFO that data is written into). Once high, STPA indicates that the transmit FIFO is not full. When STPA transitions low, it optionally indicates that the transmit FIFO is full or near full (TPALWM[7:0] register bits). STPA always provide status indication for the selected PHY in order to avoid FIFO overflows while polling is performed. The PHY Layer device shall tristate STPA when TENB is deasserted. STPA shall also be tristated when either the null-PHY address (0x7H) or an address not matching the address set by PHY_ADR[2:0] is presented on the TADR[2:0] signals when TENB is sampled high (deasserted during the previous clock cycle). STPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. STPA is tristated in byte-level transfer mode. STPA is updated on the rising edge of TFCLK. TFCLK Input (ATM) K20 UTOPIA Transmit FIFO Write Clock (TFCLK). This signal is used to write ATM cells to the four cell transmit FIFOs. TFCLK cycles at a 50 MHz or lower instantaneous rate. TFCLK Input (POS) K20 POS-PHY Transmit FIFO Write Clock (TFCLK). This signal is used to write packet octets into the 256 bytes packet FIFO’s. TFCLK cycles at a 50 MHz or lower instantaneous rate. |
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