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TDA4VM21 Datasheet(PDF) 321 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 321 Page - Texas Instruments |
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321 / 331 page  • (Connections for Unused Pins): Updated/Changed "All VMON and power balls must be …" Note deleting "VMON and"................................................................................................................................................... 150 • (Pin Connectivity Requirements): Updated/Changed the section title (was "Connections for Unused Pins") 150 • (Connectivity Requirements (ALF Package)): Updated/Changed the table title (was "Unused Balls Specific Connection Requirements")............................................................................................................................150 • (Pin Connectivity Requirements): Added "as a boot source" to the Note specifying MMC1_SDCD and MMC2_SDCD should be pulled down to work properly................................................................................. 150 • (Absolute Maximum Ratings): Moved "VMON_IR_VEXT" and "VMON_ER_VSYS"signals from "Steady State Max. Voltage at all other IO pins" to "Steady State Max. Voltage at all fail-safe IO pins".............................. 153 • Added the "VMON_IR_VEXT" and "VMON_ER_VSYS"signals to the "Fail-safe IO terminals are designed …" paragraph....................................................................................................................................................... 153 • (Absolute Maximum Ratings): Updated/Changed "JESD78D (Class II)" to " JESD78E (Class II)" in the "For current pulse injection: .." footnote................................................................................................................. 153 • (Abs Max Ratings): Updated/Changed the UNIT specified for the Latch-Up Performance MAX parameter from "mV" to "V"......................................................................................................................................................153 • (ESD Ratings): Added the AEC - Q100 document revision letter to both HBM and CDM rows.....................157 • (Power-On-Hour (POH) Limits): Updated footnotes content to match within the device family..................... 157 • (I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics): Updated/Changed the VOL, Output low- level voltage under the 3.3-V MODE MAX value from "0.4 × VDDSHV" to "0.4" V........................................161 • (I2C OD FS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODE............................................................................................. 161 • (I2C OD FS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODE........................................................... 161 • (I2C OD FS Electrical Characteristics): Added associated "I2C Hs-mode is not supported …" footnote to the 3.3-V MODE table section.............................................................................................................................. 161 • (I2C OD FS Electrical Characteristics): Added associated "The IOL parameter defines …" footnote to the IOL, low level output current parameter for both 1.8-V MODE and 3.3-V MODE.................................................. 161 • (SDIO Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODE................................................................................................. 161 • (SDIO Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODE............................................................................. 161 • (CSI-2/DSI D-PHY Electrical Characteristics): Deleted the Electrical Characteristics table and updated the Note for the CSI-2/DSI D-PHY interfaces electrical characteristics compliance with MIPI D-PHY v1.2 dated August 1, 2014............................................................................................................................................... 161 • (LVCMOS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODE................................................................................................. 161 • (LVCMOS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODE........................................................... 161 • (LVCMOS Electrical Characteristics): Added a footnote to explain the IOL and IOH parameters.................... 161 • (USB2PHY Electrical Characteristics): Added missing content......................................................................161 • (Electrical Characteristics) Added a "2-L-PHY SERDES REFCLK Electrical Characteristics" table and clarification content with reference to the device-specific Silicon Errata doc................................................. 161 • (2-L-PHY SERDES REFCLK Electrical Characteristics): Added missing table..............................................161 • (Electrical Characteristics): Moved and added titles for UFS M-PHY, eDP/DP AUX-PHY, and DDR0 Electrical Characteristics content................................................................................................................................... 161 • (WKUP_OSC0 Switching Characteristics – Crystal Mode): Updated/Changed CXIXO, XI to XO Mutual Capacitance MAX value from "0.9fF" to "0.1pF"............................................................................................ 195 • (WKUP_LFOSC0 Internal Oscillator Clock Source): Updated/Changed the ESR row UNIT column from "Ω" to "kΩ" in the WKUP_LFOSC0 Crystal Electrical Characteristics table..............................................................203 • (LFXOSC Modes of Operation table): Updated/Changed the value of PD_C for BYPASS mode from "X" to "0"................................................................................................................................................................... 203 • (DDRSS): Added a bullet below the JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices features currently supported bullets............................................................................................................... 221 www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 321 Product Folder Links: TDA4VM-Q1 TDA4VM |
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