TDA4VM21 datasheet(222/331 Pages) TI

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Table 6-51. DPI Video Output Switching Characteristics (continued)

NO.(2)

PARAMETER

MIN

MAX

UNIT

tw(pclkL)

Pulse duration, VOUT(x)_PCLK low

0.475×P(1)

tw(pclkH)

Pulse duration, VOUT(x)_PCLK high

0.475×P(1)

td(pclkV-dataV)

Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0]

transition

-0.68

1.78

td(pclkV-ctrlL)

Delay time, VOUT(x)_PCLK transition to control signals

VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge

-0.68

1.78

(1)

P = output VOUT(x)_PCLK period in ns.

(2)

x in VOUT(x) = 1 or 2

VOUT(x)_PCLK

VOUT(x)_VSYNC

VOUT(x)_HSYNC

VOUT(x)_DATA[23:0]

VOUT(x)_DE

data_1 data_2

data_n

DPI_TIMING_01

VOUT

_PCLK

(x)

Falling-edge Clock Reference

Rising-edge Clock Reference

The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.

The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)

section in Peripherals chapter in the device TRM.

The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.

x in VOUT(x) = 1 or 2.

Figure 6-54. DPI Video Output

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

222

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