TDA4VM21 datasheet(220/331 Pages) TI

220 / 331 page

see Figure 6-52

NO.

PARAMETER

MODE

MIN

TYP

MAX

UNIT

RGMII8 tw(txcL)

Pulse duration, RGMII[x]_TXC low

10Mbps

160

240

100Mbps

1000Mbps

3.6

4.4

6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode

see Figure 6-52

NO.

PARAMETER

MODE

MIN

MAX UNIT

RGMII9

tosu(tdV-txcV)

Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC

transition

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

tosu(tx_ctlV-txcV)

Output setup time, RGMII[x]_TX_CTL valid to

RGMII[x]_TXC transition

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

RGMII1

toh(tdV-txcV)

Output hold time, RGMII[x]_TD[3:0] valid after

RGMII[x]_TXC transition

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

toh(tx_ctlV-txcV)

Output hold time, RGMII[x]_TX_CTL valid after

RGMII[x]_TXC transition

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

RGMII[x]_TXC

(A)

RGMII[x]_TD[3:0]

(B)

RGMII[x] TX_CTL

(B)

RGMII9

1st Half-byte

TXERR

TXEN

2nd Half-byte

RGMII7

RGMII8

RGMII6

RGMII10

TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC

and RTXERR on falling edge of RGMII_TXC.

Figure 6-52. CPSW9G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics

- RGMII Mode

6.9.5.5 CSI-2

Note

For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the

device TRM.

The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from

memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and

still image capture.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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