TDA4VM21 datasheet(216/331 Pages) TI

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Table 6-44 represents CPSW9G timing conditions.

Table 6-44. CPSW9G Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input signal slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

6.9.5.4.1 CPSW9G MDIO Interface Timings

Table 6-45, Table 6-46, and Figure 6-47 present timing requirements and switching characteristics for MDIO.

Table 6-45. CPSW9G MDIO Timing Requirements

NO.

PARAMETER(1)

MIN

MAX

UNIT

MDIO1 tsu(mdioV-mdcH)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(mdcH-mdioV)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 6-46. CPSW9G MDIO Switching Characteristics

NO.

PARAMETER(1)

MIN

MAX

UNIT

MDIO3 tc(mdc)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(mdcH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(mdcL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(mdcL-mdioV)

Delay time, MDIO[x]_MDC falling edge to MDIO[x]_MDIO valid

-150

150

(1)

x = 0

MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 6-47. CPSW9G MDIO Diagrams Receive and Transmit

6.9.5.4.2 CPSW9G RMII Timings

Table 6-47, Section 6.9.5.4.2.1, Section 6.9.5.4.2.2, and Figure 6-48 present timing requirements for CPSW9G

RMII receive.

Table 6-47. CPSW9G RMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDDSHVx(1) = 1.8V

0.108

0.54

V/ns

VDDSHVx(1) = 3.3V

0.4

1.2

V/ns

OUTPUT CONDITIONS

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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