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TDA4VM21 Datasheet(PDF) 217 Page - Texas Instruments

Part # TDA4VM21
Description  TDA4VM Processors
PDF  331 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TDA4VM21 Datasheet(HTML) 217 Page - Texas Instruments

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Table 6-47. CPSW9G RMII Timing Conditions (continued)
PARAMETER
MIN
MAX
UNIT
CL
Output load capacitance
3
25
pF
(1)
x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information on IO power rail assinments.
6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 6-48
NO.
MIN
TYP
MAX
UNIT
RMII1
tc(ref_clk)
Cycle time, RMII[x]_REF_CLK
19.999
20.001
ns
RMII2
tw(ref_clkH)
Pulse Duration, RMII[x]_REF_CLK high
7
13
ns
RMII3
tw(ref_clkL)
Pulse Duration, RMII[x]_REF_CLK low
7
13
ns
RMII[x]_REF_CLK
RMII2
RMII3
RMII1
Figure 6-48. RMII[x]_REF_CLK Timing Requirements – RMII Mode
6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX UNIT
RMII4
tsu(rxdV-ref_clkH)
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising
edge
4
ns
tsu(crs_dvV-ref_clkH)
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising
edge
4
ns
tsu(rx_erV-ref_clkH)
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising
edge
4
ns
RMII5
th(ref_clkH-rxdV)
Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising
edge
2
ns
th(ref_clkH-crs_dvV)
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising
edge
2
ns
th(ref_clkH-rx_erV)
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge
2
ns
RMII4
RMII5
RMII[x]_
_
REF CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 6-49. CPSW9G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing Requirements – RMII
Mode
Section 6.9.5.4.2.3 and present switching characteristics for CPSW9G RMII transmit.
www.ti.com
TDA4VM-Q1, TDA4VM
SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VM-Q1 TDA4VM



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