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6.9.5.3.2 CPSW2G RMII Timings

Table 6-42, Section 6.9.5.3.2.1, Section 6.9.5.3.2.2, and Section 6.9.5.3.2.3 present timing conditions,

requirements, and switching characteristics for CPSW2G RMII.

Table 6-42. CPSW2G RMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input signal slew rate

VDDSHVx(1) = 1.8V

0.2

0.54

V/ns

VDDSHVx(1) = 3.3V

0.8

1.2

V/ns

OUTPUT CONDITIONS

Output load capacitance

(1)

x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information

on IO power rail assinments.

6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode

see Figure 6-42

NO.

MIN

MAX

UNIT

RMII1

tc(ref_clk)

Cycle time, RMII[x]_REF_CLK

19.999

20.001

RMII2

tw(ref_clkH)

Pulse Duration, RMII[x]_REF_CLK high

RMII3

tw(ref_clkL)

Pulse Duration, RMII[x]_REF_CLK low

RMII[x]_REF_CLK

RMII2

RMII3

RMII1

x = 1 in MCU domain.

Figure 6-42. CPSW2G RMII[x]_REFCLK Timing Requirements – RMII Mode

6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode

NO.

MIN

MAX

UNIT

RMII4

tsu(rxdV-ref_clkH)

Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising

edge

tsu(crs_dvV-ref_clkH)

Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising

edge

tsu(rx_erV-ref_clkH)

Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising

edge

RMII5

th(ref_clkH-rxdV)

Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising

edge

th(ref_clkH-crs_dvV)

Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising

edge

th(ref_clkH-rx_erV)

Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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