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TDA4VM21 Datasheet(PDF) 210 Page - Texas Instruments

Part # TDA4VM21
Description  TDA4VM Processors
PDF  331 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TDA4VM21 Datasheet(HTML) 210 Page - Texas Instruments

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6.9.5.2 VPFE
Table 6-37 represents VPFE timnig conditions.
Table 6-37. VPFE Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
1.3
2.64
V/ns
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch across
all traces
50
ps
Table 6-38, Figure 6-39, and Figure 6-40 represent timing requirements for VPFE0.
Table 6-38. Timing Requirements for VPFE0
NO.(1)
MIN
MAX
UNIT
V1
tc(pclk)
Cycle time, VPFE0_PCLK
6.06(1)
ns
V2
tw(pclkH)
Pulse duration, VPFE0_PCLK high
0.45 × P(2)
ns
V3
tw(pclkL)
Pulse duration, VPFE0_PCLK low
0.45 × P(2)
ns
V4
tsu(ctrlV-pclkV)
Setup time, control signals (VPFE0_HD, VPFE0_VD,
VPFE0_WEN, VPFE0_FIELD) valid before VPFE0_PCLK
transition
2.12
ns
V5
tsu(dataV-pclkV)
Setup time, VPFE0_DATA[15:0] valid before VPFE0_PCLK
transition
2.38
ns
V6
th(pclkV-ctrlV/dataV)
Hold time, control signals (VPFE0_HD, VPFE0_VD, VPFE0_WEN,
VPFE0_FIELD) and VPFE0_DATA[15:0] valid after VPFE0_PCLK
transition
-0.05
ns
(1)
For maximum frequency of 165 MHz.
(2)
P = VPFE0_PCLK period.
VPFE0_TIMING_01
VPFE0_PCLK
V2
V1
V3
Figure 6-39. VPFE0 Clock Signal Requirement
VPFE0_PCLK
(Negative-edge clocking)
VPFE0_HD, VPFE0_VD,
VPFE0_WEN, VPFE0_FIELD
V4
V6
VPFE0_PCLK
(Positive-edge clocking)
VPFE0_TIMING_02
V5
V6
VPFE0_DATA[15:0]
Figure 6-40. VPFE0 Timing Requirements
For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM.
TDA4VM-Q1, TDA4VM
SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024
www.ti.com
210
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TDA4VM-Q1 TDA4VM



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