TDA4VM21 datasheet(211/331 Pages) TI

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6.9.5.3 CPSW2G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see

the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.

6.9.5.3.1 CPSW2G MDIO Interface Timings

Table 6-39 represents CPSW2G timing conditions.

Table 6-39. CPSW2G MDIO Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input signal slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

Table 6-40, Table 6-41, and Figure 6-41 present timing requirements for MDIO.

Table 6-40. CPSW2G MDIO Timing Requirements

NO.

MIN

MAX

UNIT

MDIO1 tsu(mdioV-mdcH)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(mdcH-mdioV)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 6-41. CPSW2G MDIO Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

MDIO3 tc(mdc)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(mdcH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(mdcL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(mdcL-mdioV)

Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid

-150

150

MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 6-41. CPSW2G MDIO Timing Requirements and Switching Characteristics

Note

x = 0 in MCU domain

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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