TDA4VM21 datasheet(227/331 Pages) TI

227 / 331 page

NO.

MIN

MAX UNIT

QEP5

tw(qepsL)

Pulse duration, QEP_S low

2 + 2P(1)

(1)

P = sysclk

QEP_S

QEP4

EPERIPHERALS_TIMNG_03

QEP_I

QEP2

QEP_A/B

QEP1

QEP3

QEP5

Figure 6-62. eQEP Input Timings

6.9.5.10.2 Switching Characteristics for eQEP

NO.

PARAMETER

MIN

MAX UNIT

QEP6

td(QEP-CNTR)

Delay time, external clock to counter increment

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter

in the device TRM.

6.9.5.11 GPIO

The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.

• Group one: WKUP_GPIO0 and WKUP_GPIO1

• Group two: GPIO0, GPIO2, GPIO4, and GPIO6

• Group three: GPIO1, GPIO3, GPIO5, and GPIO7

Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts.

The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up

to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface

supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),

GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general

purpose interface supports up to 248 I/O pins.

For more details about features and additional description information on the device General-Purpose Interface,

see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.

Note

The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.

Table 6-56 represents GPIO timing conditions.

Table 6-56. GPIO Timing Conditions

PARAMETER

BUFFER TYPE

MIN

MAX UNIT

INPUT CONDITIONS

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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