TDA4VM21 datasheet(230/331 Pages) TI

230 / 331 page

NO.(2) PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX

MIN

MAX UNI

100 MHz(20)

133 MHz(20)

td(be[x]nV-clk)

Delay time, output lower byte enable and

command latch enable GPMC_BE0n_CLE,

output upper byte enable GPMC_BE1n

valid to output clock GPMC_CLK first edge

div_by_1_mode

B(2)-2.3 B(2)+1.9

B(2)-2.3 B(2)+1.9 ns

td(clkH-be[x]nIV)

Delay time, output clock GPMC_CLK rising

edge to output lower byte enable and

command latch enable GPMC_BE0n_CLE,

output upper byte enable GPMC_BE1n

invalid(11)

div_by_1_mode

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(12)

div_by_1_mode

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

td(clkL-be[x]nIV).

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(13)

div_by_1_mode

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

td(clkH-advn)

Delay time, output clock GPMC_CLK rising

edge to output address valid and address

latch enable GPMC_ADVn_ALE transition

div_by_1_mode

no extra_delay

G(7)-2.3 G(7)+4.5

G(7)-2.3 G(7)+4.5 ns

td(clkH-advnIV)

Delay time, output clock GPMC_CLK rising

edge to output address valid and address

latch enable GPMC_ADVn_ALE invalid

div_by_1_mode;

no extra_delay

D(4)-2.3 D(4)+4.5

D(4)-2.3 D(4)+4.5 ns

F10

td(clkH-oen)

Delay time, output clock GPMC_CLK rising

edge to output enable GPMC_OEn_REn

transition

div_by_1_mode

no extra_delay

H(8)-2.3 H(8)+3.5

H(8)-2.3 H(8)+3.5 ns

F11

td(clkH-oenIV)

Delay time, output clock GPMC_CLK rising

edge to output enable GPMC_OEn_REn

invalid

div_by_1_mode

no extra_delay

E(8)-2.3 E(8)+3.5

E(8)-2.3 E(8)+ 3.5 ns

F14

td(clkH-wen)

Delay time, output clock GPMC_CLK rising

edge to output write enable GPMC_WEn

transition

div_by_1_mode

no extra_delay

I(9)- 2.3

I(9)+4.5

I(9)- 2.3

I(9)+4.5 ns

F15

td(clkH-do)

Delay time, output clock GPMC_CLK

rising edge to output data GPMC_AD[15:0]

transition(11)

div_by_1_mode

J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns

F15

td(clkL-do)

Delay time, GPMC_CLK falling edge to

GPMC_AD[15:0] data bus transition(12)

div_by_1_mode

J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns

F15

td(clkL-do).

Delay time, GPMC_CLK falling edge to

GPMC_AD[15:0] data bus transition(13)

div_by_1_mode

J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns

F17

td(clkH-be[x]n)

Delay time, output clock GPMC_CLK rising

edge to output lower byte enable and

command latch enable GPMC_BE0n_CLE

transition(11)

div_by_1_mode

J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns

F17

td(clkL-be[x]n)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition(12)

div_by_1_mode

J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns

F17

td(clkL-be[x]n).

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition(13)

div_by_1_mode

J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns

F18

tw(csnV)

Pulse duration, output chip select

GPMC_CSn[i] low(14)

Read

A(1)

Write

A(1)

F19

tw(be[x]nV)

Pulse duration, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n low

Read

C(3)

Write

C(3)

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

230

Submit Document Feedback

Product Folder Links: TDA4VM-Q1 TDA4VM

TDA4VM21 Datasheet(PDF) 230 Page - Texas Instruments

TDA4VM21 Datasheet(HTML) 230 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL