TDA4VM21 datasheet(229/331 Pages) TI

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6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode

Section 6.9.5.12.1.1 and Section 6.9.5.12.1.2 assume testing over the recommended operating conditions and

electrical characteristic conditions below (see Figure 6-63 through Figure 6-67).

6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode

NO.

PARAMETER

DESCRIPTION

(2)

MODE

(3)

MIN

MAX

MIN

MAX

UNIT

100 MHz

(4)

133 MHz

(4)

F12 tsu(dV-clkH)

Setup time, input data

GPMC_AD[15:0] valid before

output clock GPMC_CLK high

div_by_1_mode;

1.81

1.11

not_div_by_1_mode;

1.06

F13 th(clkH-dV)

Hold time, input data

GPMC_AD[15:0] valid after

output clock GPMC_CLK high

div_by_1_mode;

1.78

2.28

not_div_by_1_mode;

1.78

F21 tsu(waitV-clkH)

Setup time, input wait

GPMC_WAIT[j] valid before

output clock GPMC_CLK high

(1)

div_by_1_mode;

1.81

1.11

not_div_by_1_mode;

1.06

F22 th(clkH-waitV)

Hold time, input wait

GPMC_WAIT[j] valid after output

clock GPMC_CLK high

(1)

div_by_1_mode;

1.78

2.28

not_div_by_1_mode;

1.78

(1)

In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.

(2)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

(3)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

•

(4)

For 100 MHz:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3

For 133 MHz:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT

6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.(2) PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX

MIN

MAX UNI

100 MHz(20)

133 MHz(20)

tc(clk)

Period, output clock GPMC_CLK(18)

div_by_1_mode;

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode

0.475*P

(15)- 0.3

0.475*P

(15)- 0.3

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode

0.475*P

(15)- 0.3

0.475*P

(15)- 0.3

td(clkH-csnV)

Delay time, output clock GPMC_CLK rising

edge to output chip select GPMC_CSn[i]

transition(14)

div_by_1_mode

no extra_delay

F(6)-2.2

F+3.75

F(6)-2.2 F(6)+3.75 ns

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK rising

edge to output chip select GPMC_CSn[i]

invalid(14)

div_by_1_mode

no extra_delay

E(5)-2.2 E(5)+3.75

E(5)-2.2

(5)+3.75

td(aV-clk)

Delay time, output address GPMC_A[27:1]

valid to output clock GPMC_CLK first edge

div_by_1_mode

B(2)-2.3 B(2)+4.5

B(2)-2.3 B(2)+4.5 ns

td(clkH-aIV)

Delay time, output clock GPMC_CLK rising

edge to output address GPMC_A[27:1]

invalid

div_by_1_mode;

-2.3

4.5

-2.3

4.5 ns

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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