PM7385 datasheet(49/244 Pages) PMC

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PM7385 FREEDM-84A672

DATA SHEET

PMC-1990114

ISSUE 6

84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

WITH ANY-PHY PACKET INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

frequency and alignment as determined by the reference clock (REFCLK) and

frame indicator signal (C1FP). Frequency deviations are compensated by

adjusting the location of the T1/J1/E1/DS3 channels using floating tributaries as

determined by the V5 indicator and payload signals (DV5, AV5, DPL and APL).

The multiplexed links are separated into three Synchronous Payload Envelopes.

Each envelope may be configured independently to carry up to 28 T1/J1s, 21

E1s or a DS3.

8.2 High-Level Data Link Control (HDLC) Protocol

Figure 1 shows a diagram of the synchronous HDLC protocol supported by the

FREEDM-84A672 device. The incoming stream is examined for flag bytes

(01111110 bit pattern) which delineate the opening and closing of the HDLC

packet. The packet is bit de-stuffed which discards a “0” bit which directly follows

five contiguous “1” bits. The resulting HDLC packet size must be a multiple of an

octet (8 bits) and within the expected minimum and maximum packet length

limits. The minimum packet length is that of a packet containing two information

bytes (address and control) and FCS bytes. For packets with CRC-CCITT as

FCS, the minimum packet length is four bytes while those with CRC-32 as FCS,

the minimum length is six bytes. An HDLC packet is aborted when seven

contiguous “1” bits (with no inserted “0” bits) are received. At least one flag byte

must exist between HDLC packets for delineation. Contiguous flag bytes, or all

ones bytes between packets are used as an “inter-frame time fill”. Adjacent flag

bytes may share zeros.

Figure 1 – HDLC Frame

Flag

Information

FCS

Flag

HDLC Packet

Flag

The CRC algorithm for the frame checking sequence (FCS) field is either a

CRC-CCITT or CRC-32 function. Figure 2 shows a CRC encoder block diagram

using the generating polynomial g(X) = 1 + g1X + g2X2 +…+ gn-1Xn-1 + Xn. The

CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +

X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating

polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22

+ X23 + X26 + X32. The first FCS bit received is the residue of the highest term.

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