PM7385 datasheet(16/244 Pages) PMC

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PM7385 FREEDM-84A672

DATA SHEET

PMC-1990114

ISSUE 6

84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

WITH ANY-PHY PACKET INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

selection. The external controller is also the master for channel selection in the

transmit direction. In the receive direction, however, each FREEDM-84A672

device retains control over selection of its respective channels. The transmit and

receive APPI is made up of three groups of functional signals – polling, selection

and data transfer. The polling signals are used by the external controller to

interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.

The selection signals are used by the external controller to select a FREEDM-

84A672 device, or a channel within a FREEDM-84A672 device, for data transfer.

The data transfer signals provide a means of transferring data across the APPI

between the external controller and a FREEDM-84A672 device.

In the receive direction, polling and selection are done at the device level.

Polling is not decoupled from selection, as the receive address pins serve as

both a device poll address and to select a FREEDM-84A672 device. In response

to a positive poll, the external controller may select that FREEDM-84A672 device

for data transfer. Once selected, the FREEDM-84A672 prepends an in-band

channel address to each partial packet transfer across the receive APPI to

associate the data with a channel. A FREEDM-84A672 must not be selected

after a negative poll response.

In the transmit direction, polling is done at the channel level. Polling is

completely decoupled from selection. To increase the polling bandwidth, up to

two channels may be polled simultaneously. The polling engine in the external

controller runs independently of other activity on the transmit APPI. In response

to a positive poll, the external controller may commence partial packet data

transfer across the transmit APPI for the successfully polled channel of a

FREEDM-84A672 device. The external controller must prepend an in-band

channel address to each partial packet transfer across the transmit APPI to

associate the data with a channel.

In the receive direction, the FREEDM-84A672 performs channel assignment and

packet extraction and validation. For each provisioned HDLC channel, the

FREEDM-84A672 delineates the packet boundaries using flag sequence

detection, and performs bit de-stuffing. Sharing of opening and closing flags, as

well as sharing of zeros between flags are supported. The resulting packet data

is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet

buffer acts as a logical FIFO for each of the assigned channels. An external

controller transfers partial packets out of the RAM, across the receive APPI bus,

into host packet memory. The FREEDM-84A672 validates the frame check

sequence for each packet, and verifies that the packet is an integral number of

octets in length and is within a programmable minimum and maximum lengths.

Receive APPI bus latency may cause one or more channels to overflow, in which

case, the packets are aborted. The FREEDM-84A672 reports the status of each

packet on the receive APPI at the end of each packet transfer.

PM7385 Datasheet(PDF) 16 Page - PMC-Sierra, Inc

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