PM7385 datasheet(61/244 Pages) PMC

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PM7385 FREEDM-84A672

DATA SHEET

PMC-1990114

ISSUE 6

84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

WITH ANY-PHY PACKET INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

8.8 Transmit HDLC Controller / Partial Packet Buffer

The Transmit HDLC Controller / Partial Packet Buffer block (THDL672) contains

a partial packet buffer for Tx APPI latency control and a transmit HDLC controller.

The THDL672 also contains logic to monitor the full/empty status of each channel

FIFO and push this status onto the polling interface signals.

The THDL672 requests data from the TAPI672 in response to control information

from the TAPI672 indicating the channel for which data is available and ready to

be transferred. Packet data received from the TAPI672 is stored in channel

specific FIFOs residing in the partial packet buffer. When the amount of data in a

FIFO reaches a programmable threshold, the HDLC controller is enabled to

initiate transmission. The HDLC controller performs flag generation, bit stuffing

and, optionally, frame check sequence (FCS) insertion. The FCS is software

selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding

FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers

data to the Transmit Channel Assigner block (TCAS672) on demand. A packet in

progress is aborted if an under-run occurs. The THDL672 is programmable to

operate in transparent mode where packet data retrieved from the TAPI672 is

transmitted verbatim.

8.8.1 Transmit HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 672

independent channels. The state vector and provisioning information for each

channel is stored in a RAM. Whenever the TCAS672 requests data, the

appropriate state vector is read from the RAM, processed and finally written back

to the RAM. The HDLC state-machine can be configured to perform flag

insertion, bit stuffing and CRC generation. The HDLC processor requests data

from the partial packet processor whenever a request for channel data arrives.

However, the HDLC processor does not start transmitting a packet until the entire

packet is stored in the channel FIFO or until the FIFO free space is less than the

software programmable limit. If a channel FIFO under-runs, the HDLC processor

aborts the packet, generates a microprocessor interrupt and signals the

underflow to the transmit Any-PHY interface.

The configuration of the HDLC processor is accessed using indirect channel read

and write operations. When an indirect operation is performed, the information is

accessed from RAM during a null clock cycle inserted by the TCAS672 block.

Writing new provisioning data to a channel resets the channel’s entire state

vector.

PM7385 Datasheet(PDF) 61 Page - PMC-Sierra, Inc

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