LX7220

DS20006704A-page 6

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TABLE 1-1:

I2C TIMING SPECIFICATIONS

Parameter

Sym.

Cb = 100 pF

(max) (Note 2)

Cb = 400 pF

Units

Conditions

Min.

Max.

Min.

Max.

SCL clock frequency

fSCHL

0

3.4

0

0.4

MHz

Set-up time for a repeated

START condition

tSU;STA

160

—

600

—

ns

Hold time (repeated) START

condition

tHD;STA

160

—

600

—

ns

LOW period of the SCL clock

tLOW

160

—

1300

—

ns

HIGH period of the SCL clock

tHIGH

60

—

600

—

ns

Data set-up time

tSU;DAT

10

—

100

—

ns

Data hold time

tHD;DAT

070

0

—

ns

Rise time of SCL signal

trCL

10

40

20 × 0.1Cb

300

ns

Rise time of SCL signal after a

repeated START condition and

after an acknowledge bit

trCL1

10

80

20 × 0.1Cb

300

ns

Fall time of SCL signal

tfCL

10

40

20 × 0.1Cb

300

ns

Rise time of SDA signal

trDA

10

80

20 × 0.1Cb

300

ns

Fall time of SDA signal

tfDA

10

80

20 × 0.01Cb 300

ns

Set-up time for STOP

condition

tSU;STO

160

—

600

—

ns

Bus free time between a STOP

and START condition

tBUF

160

—

1300

—

ns

Data valid time

tVD;DAT

—

160

—

900

ns

Data valid acknowledge time

tVD;ACK

—

160

—

900

ns

Capacitive load for each bus line

Cb

—

100

—

400

pF

SDA and SCL lines

Note 1: All values referred to VIH(min) and VIL(max) levels of I/O stages table.

2: Loads in excess of 100 pF will restrict bus operation speed below 3.4 MHz.