LX7220 datasheet(11/24 Pages) MICROCHIP

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DS20006704A-page 11

LX7220

4.7

I2C Electrical Characteristics

The minimum HIGH and LOW periods of the SCL clock

specified the I2C Timing Specification table determine

the maximum bit transfer rates of, 400 kbits/s for

Fast-mode devices, and 3.4 Mbits/s for HS-mode Plus.

Devices must be able to follow transfers at their own

maximum bit rates, either by being able to transmit or

receive at that speed or by applying the I2C clock

synchronization procedure, which will force the host

into a wait state and stretch the LOW period of the SCL

signal. Of course, in the latter case the bit transfer rate

is reduced.

Figure 4-3 and Figure 4-4 show all timing parameters

for the HS & FS-mode timing. The ‘normal’ START

condition S does not exist in HS-mode. Timing

parameters for Address bits, R/W bit, Acknowledge bit

and DATA bits are all the same. Only the rising edge of

the first SCL clock signal after an acknowledge bit has

a larger value because the external Rp has to pull-up

SCL without the help of the internal current-source.

The HS & FS-mode timing parameters for the bus lines

are specified in the Table 1-1. The minimum HIGH and

LOW periods and the maximum rise and fall times of

the SCL clock signal determine the highest bit rate.

With an internally generated SCL signal with LOW and

HIGH level periods of 200 ns and 100 ns respectively,

an HS-mode host fulfills the timing requirements for the

external SCL clock pulses (taking the rise and fall times

into account) for the maximum bit rate of 3.4 Mbit/s. So

a basic frequency of 10 MHz, or a multiple of 10 MHz,

can be used by an HS-mode host to generate the SCL

signal. There are no limits for maximum HIGH and

LOW periods of the SCL clock, and there is no limit for

a lowest bit rate.

Timing parameters are independent for capacitive load

up to 100 pF for each bus line allowing the maximum

possible bit rate of 3.4 Mbit/s. At a higher capacitive

load on the bus lines, the bit rate decreases gradually.

The timing parameters for a capacitive bus load of

400 pF are specified in Table 1-1, allowing a maximum

bit rate of 1.7 Mbit/s. For capacitive bus loads between

100 pF and 400 pF, the timing parameters must be

interpolated linearly. Rise and fall times are in

accordance with the maximum propagation time of the

transmission lines SDA and SCL to prevent reflections

of the open ends.

FIGURE 4-1:

Write Protocol.

FIGURE 4-2:

Read Protocol.

FIGURE 4-3:

Definition for FS-Mode Devices on the I2C Port.

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