LX7220 datasheet(10/24 Pages) MICROCHIP

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LX7220

DS20006704A-page 10

 2022 Microchip Technology Inc. and its subsidiaries

4.0

I2C INTERFACE

I2C Port Functional Description

• Simple two wire, bidirectional, serial

communication port.

• Multiple devices on same bus speeds from

400 kbps (FS-Mode) to 3.4 Mbps (HS-Mode).

• SOC Host controls bus.

• Device listens for the unique address that

precedes data.

4.1

General I2C Port Description

LX7220 includes an I2C compatible serial interface,

using two dedicated pins: SCL and SDA for I2C clock

and data respectively. Each line is externally pulled up

to a logic voltage when they are not being controlled by

a device on the bus. The LX7220 interface acts as an

I2C client that is clocked by the incoming SCL clock.

The LX7220 I2C port will support both the Fast mode

(400 kHz max) and typically the High Speed mode

(3.4 MHz max). The data on the SDA line must be

stable during the HIGH period of the clock signal (SCL).

The state of the SDA line can only be changed when

SCL is LOW (except for start, stop, and restart).

4.2

LX7220 has five 8-bit user-accessible registers. See

Control Register Bit Definition.

4.3

Client Address

In the table below, the A1 and A0 are the binary value

of the address given in the ordering information for the

“x” value shown in Ordering Information.

4.4

START and STOP Commands

When the bus is idle, both SCL and SDA must be high

except in the power up case where they may be held

high or low during the system power up sequence.

The STX SOC (bus host) signals START and STOP

bits signify the beginning and the end of the I2C

transfer. The START condition is defined as the SDA

signal transitioning from HIGH to LOW while the SCL

line is HIGH. The STOP condition is defined as the

SDA transitioning from LOW to HIGH while the SCL is

HIGH. The STX SOC acts as the I2C host and always

generates the START and STOP bits. The I2C bus is

considered to be busy after START condition and free

after STOP condition. During data transfer, STX SOC

host can generate repeated START conditions. The

START and the repeated START conditions are

functionally equivalent.

4.5

Data Transfers

Data is transferred in 8-bit bytes by SDA with the MSB

transferred first. Each byte of data has to be followed by

an acknowledge (ACK) bit. The acknowledged related

clock pulse is generated by the host. The acknowledge

occurs when the transmitter host releases the SDA line

to a high state during the acknowledge clock. The SDA

line must be pulled down by the receiver client during

the 9th clock pulse to signify acknowledgment. A

receiver client which has been addressed must

generate an acknowledgement (“ACK”) after each byte

has been received.

After the START condition, the STX SOC (I2C) host

sends a chip address. The standard I2C address is

seven bits long. Making the eighth bit a data direction

bit (R/W). For the eighth bit (LSB), a “0” indicates a

WRITE and a “1” indicates a READ. (For clarification,

communications are broken up into 9-bit segments,

one byte followed by one bit for acknowledging.) The

second byte selects the register to which the data will

be written. The third byte contains data to write to the

selected register.

When a receiver client does not acknowledge the client

address, the data line must be left HIGH by the client.

The host can then generate a STOP command to abort

the transfer. If a client receiver does acknowledge the

client address but, sometime later in the transfer can-

not receive any more data bytes, the host must again

abort the transfer.

This is indicated by the client generating the not

acknowledge on the first byte to follow.

The client leaves the data line HIGH and the host

generates the STOP command. The data line is also

left high by the client and host after a client has

transmitted a byte of data to the host in a read

operation, but this is a not acknowledge that indicates

that the data transfer is successful.

4.6

Data Transfer Timing for Write

Commands

In order to help assure that bad data is not written into

the part, data from a write command is only stored after

a valid STOP command has been performed.

TABLE 4-1:

I2C CLIENT ADDRESS

76543210

11100

R/W

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