LX7220 datasheet(8/24 Pages) MICROCHIP

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LX7220

DS20006704A-page 8

 2022 Microchip Technology Inc. and its subsidiaries

3.0

OPERATION THEORY

3.1

Basic Operation

The LX7220 compares VOUT voltage to an internal

reference, VREF. When VOUT is lower than VREF, the

upper switch turns on and the lower switch turns off.

When VOUT is higher than VREF, the upper switch turns

off and the lower switch turns on. An internal ramp

helps to keep the switching frequency constant over a

wide range of output capacitor values and parasitic

components (i.e. ESR, ESL). In addition, a frequency

control loop keeps the switching frequency constant

during continuous conduction mode.

At light loads, if enabled, the converter automatically

reduces

the

switching

frequency

and

enters

discontinuous conduction mode to optimize efficiency

while ensuring low VOUT ripple voltage.

An integrated I2C bus interface, operating up to

3.4 Mbps, adds the following use programmability to

the converter:

On-the-fly programming of the output voltage in

4.7 mV increments

Enable/Disable the regulator

Allow PSM or limit operation to PWM only mode

Set the VREF slew rate

Switch node slew rate control.

3.2

Setting the Output Voltage

The output voltage is set with the reference voltage and

how the VOUT pin (12) is connected to the output. With

a direct connection (see Typical Application Circuit),

the reference voltage equals the output voltage. When

the VOUT pin (12) is connected to a resistor divider,

this also determines the output voltage. At start-up, the

reference voltage is determined by the parts number “y”

parameter (i.e. LX7220-xyILQ); “y” sets the output

voltage (3 is 0.95V, 2 is 0.9V). After start-up, the

reference voltage can be programmed with the I2C bus

VSEL register value.

The output voltage is determined as follows:

3.3

Start-Up

If the LX7220 is enabled, when VIN rises above the

UVLO threshold, the regulator will initiate a start-up

sequence. The serial port registers are initialized to

their default values and all internal bias voltages and

currents are allowed to stabilize. VREF then ramps up

from 0V to the default voltage, at the default slew rate.

At the end of the ramp time, PGOOD is allowed to go

high after VOUT has reached the PGOOD rising

threshold. During the ramp time, the LX7220 switches

to PSM to allow discontinuous operation. This

switchover is independent of the MODE bit setting.

3.4

Overcurrent Protection

LX7220 protects against all types of short circuit

conditions. Cycle-by-cycle overcurrent protection turns

off the upper switch when the current exceeds the OCP

threshold. When this occurs, the upper switch is held

off for at least 350 ns before being allowed to turn on

again. After start-up, if VOUT drops below the VOUT

undervoltage threshold, a hiccup sequence will be initi-

ated where both output switches are shut off for 6.5 ms

before initiating another soft start cycle. This protects

against a crowbar short circuit. The VOUT undervoltage

detection is not active during start-up.

3.5

Positive Voltage Transitions

After the initial start-up sequence, the output voltage

can be programmed to a new value by programming

the VSEL register bits and then asserting the GO bit.

VREF will transition to the new value at the programmed

slew rate. The PGOK monitor bit is deasserted during

the VREF ramp time, or when VOUT is outside the error

envelope.

FIGURE 3-1:

Positive Voltage Transition.

VREF 0.6V NSEL 0.0046875V



Where:

NSEL is the decimal value of the 7 VSEL bits.

(2)

VOUT

VREF

RTOP

RBOTTOM

----------------------- 









(3)

Where:

RTOP is the resistor connected from VOUT pin to output.

RBOTTOM is the resistor connected from VOUT pin to GND.

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