ADS9813 datasheet(4/66 Pages) TI

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Table 4-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

AIN8M

Analog input channel 8, negative input.

AIN8P

Analog input channel 8, positive input.

AVDD_5V

15, 56

5V analog supply. Connect 1µF and 0.1µF decoupling capacitors to GND.

Chip-select input for the SPI interface configuration; active low. This pin has an internal

100kΩ pullup resistor to IOVDD.

Serial output data lane 0.

Serial data output lane 1.

Serial data output lane 2.

Serial data output lane 3.

DCLKOUT

Clock output for the data interface.

FCLKOUT

Frame synchronization output for the data interface.

GND

7, 23, 29, 42,

Ground.

IOVDD

30, 41

Digital I/O supply for the data interface. Connect 1µF and 0.1µF decoupling capacitors to

GND.

20, 38, 39, 50,

—

Not connected. No external connection.

PWDN

Power-down control; active low. PWDN has an internal 100kΩ pullup resistor to the digital

interface supply.

REFIO

AI/AO

REFIO acts as an internal reference output when the internal reference is enabled. REFIO

functions as an input pin for the external reference when the internal reference is disabled.

Connect a 10µF decoupling capacitor to the REFM pins.

REFM

8, 18, 53

Reference ground potential. Connect to GND.

REFOUT_2V5

2.5V reference output. Connect a decoupling 10µF capacitor to the REFM pins.

RESET

Reset input for the device; active low. RESET has an internal 100kΩ pullup resistor to the

digital interface supply.

SCLK

Serial clock input for the configuration interface. SCLK has an internal 100kΩ pulldown

resistor to the digital interface ground.

SDI/EXTREF

SDI is a multifunction logic input. Pin function is determined by the SPI_EN pin. SDI has an

internal 100kΩ pulldown resistor to GND.

SPI_EN = 0b: SDI is the logic input to select between the internal or external reference.

Connect SDI to GND for the external reference. Connect SDI to IOVDD for the internal

reference.

SPI_EN = 1b: Serial data input for the configuration interface.

SDO

Serial data output for the configuration interface.

SMPL_CLKM

Connect SMPL_CLKM to GND for a single-ended ADC sampling clock input. SMPL_CLKM

is the negative input for the differential sampling clock input to the ADC.

SMPL_CLKP

Single-ended ADC sampling clock input. SMPL_CLKP is the positive input for the differential

sampling clock input to the ADC.

SMPL_SYNC

Synchronization input. See the Synchronizing Multiple ADCs section on how to use the

SMPL_SYNC pin.

SPI_EN

Logic input to enable the SPI interface configuration (CS, SCLK, SDI, and SDO). SPI_EN

has an internal 100kΩ pullup resistor to the digital interface supply.

VDD_1V8

21, 22, 47, 48,

1.8V power-supply. Connect 1µF and 0.1µF decoupling capacitors to GND.

Thermal pad

—

Exposed thermal pad; connect to GND.

(1)

I = input, O = output, I/O = input or output, G = ground, and P = power.

ADS9813, ADS9811, ADS9810

SBASAQ6A – JULY 2024 – REVISED NOVEMBER 2024

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