ADS9813 datasheet(21/66 Pages) TI

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6.3 Feature Description

6.3.1 Analog Inputs

The ADS9813 incorporates eight, simultaneous sampling, 18-bit successive approximation register (SAR)

analog-to-digital converters (ADCs). The device has a total of eight analog input pairs. The ADC digitizes

the voltage difference between the analog input pairs AINxP – AINxM. Figure 6-1 shows the simplified

circuit schematic for each analog input channel. This figure also shows the input clamp protection circuit,

programmable gain amplifier (PGA), low-pass filter, high-speed ADC driver, and a precision 18-bit SAR ADC.

Typical SNR for analog input ranges vs input common-mode ranges are shown in Table 6-5 for low-bandwidth

mode and Table 6-6 for wide-bandwidth mode.

Clamp

AINxP

AINxM

Prog. LPF

SAR

ADC

Clamp

PGA

Figure 6-1. Front-End Circuit Schematic for the Selected Analog Input Channel

6.3.1.1 Input Clamp Protection Circuit

The ADS9813 features an internal clamp protection circuit (Figure 6-1) on each of the eight analog input

channels. The input clamp protection circuit allows each analog input to swing up to a maximum voltage of ±18V.

Beyond an input voltage of ±18V, the input clamp circuit turns on and still operates from the single 5V supply.

Figure 6-2 shows a typical current versus voltage characteristic curve for the input clamp.

For input voltages above the clamp threshold, make sure that the input current never exceeds ±10mA. A resistor

placed in series with the analog inputs is an effective way to limit the input current. In addition to limiting the input

current, the series resistor also provides an antialiasing, low-pass filter (LPF) when coupled with a capacitor.

Matching the external source impedance on the AINxP and AINxM pins cancels any additional offset error.

Input Voltage (V)

-30 -25 -20 -15 -10

-5

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

Figure 6-2. Input Protection Clamp Profile, Input Clamp Current vs Source Voltage

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ADS9813, ADS9811, ADS9810

SBASAQ6A – JULY 2024 – REVISED NOVEMBER 2024

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