ADS9813 datasheet(42/66 Pages) TI

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7.2.2 Register 13h (offset = 13h) [reset = 0h]

Figure 7-17. Register 13h

RESERVED

R/W-0h

RAMP_INC_A

TP_MODE_A

TP_EN_A

RESERVED

R/W-0h

Figure 7-18. Register 13h Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R/W

Reserved. Do not change from the default reset value.

7-4

RAMP_INC_A

R/W

Increment value for the ramp pattern output. The output

ramp increments by N+1, where N is the value configured

in this register.

3-2

TP_MODE_A

R/W

Select digital test pattern for analog input channels 1, 2, 3,

and 4.

0 : Fixed pattern from the TP0_A register

1 : Fixed pattern from the TP0_A register

2 : Digital ramp output

3 : Alternate fixed pattern output from the TP0_A and

TP1_A registers

TP_EN_A

R/W

Enable digital test pattern for data corresponding to

channels 1, 2, 3, and 4.

0 : Data output is the ADC conversion result

1 : Data output is the digital test pattern for channels 1, 2, 3,

and 4

RESERVED

R/W

Reserved. Do not change from the default reset value.

7.2.3 Register 14h (offset = 14h) [reset = 0h]

Figure 7-19. Register 14h

TP0_A[15:0]

R/W-0h

TP0_A[15:0]

R/W-0h

Figure 7-20. Register 14h Field Descriptions

Bit

Field

Type

Reset

Description

15-0

TP0_A[15:0]

R/W

Lower 16 bits of test pattern 0

ADS9813, ADS9811, ADS9810

SBASAQ6A – JULY 2024 – REVISED NOVEMBER 2024

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