AM67 datasheet(124/237 Pages) TI

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NO.

MODE

MIN

MAX UNIT

tw(bwsH)

Pulse Duration, ATL_BWS[x] high(3)

External reference

clock

0.45 × B(2) + 2.5

(1)

M = ATL_CLK[x] period

(2)

B = ATL_BWS[x] period

(3)

x = 0 to 3

6.9.5.1.4 ATCLK[x] Switching Characteristics

NO.

PARAMETER

MODE

MIN

MAX UNIT

D10 tc(atclk)

Cycle time, ATCLK[x](3)

Internal reference

CLK

D11 tw(atclkL)

Pulse Duration, ATCLK[x] low(3)

Internal reference

CLK

0.45 × P(2) - M(1) - 0.3

D12 tw(atclkH)

Pulse Duration, ATCLK[x] high(3)

Internal reference

CLK

0.45 × P(2) - M(1) - 0.3

(1)

M = ATL_CLK[x] period

(2)

P = ATCLK[x] period

(3)

x = 0 to 3

ATCLK[x]

D12

D11

D10

atl_01

Figure 6-26. ATCLK[x] Timing

6.9.5.2 CPSW3G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see

the corresponding subsections within Signal Descriptions and Detailed Description sections.

6.9.5.2.1 CPSW3G MDIO Timing

Table 6-28, Table 6-29, Table 6-30, and Figure 6-27 present timing conditions, timing requirements, and

switching characteristics for CPSW3G MDIO.

Table 6-28. CPSW3G MDIO Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

Table 6-29. CPSW3G MDIO Timing Requirements

see Figure 6-27

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 tsu(MDIO_MDC)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(MDC_MDIO)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

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