AM67 datasheet(171/237 Pages) TI

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6.9.5.17.1 MCSPI — Controller Mode

Table 6-77, Figure 6-64, Table 6-78, and Figure 6-65 present timing requirements and switching characteristics

for SPI – Controller Mode.

Table 6-77. MCSPI Timing Requirements – Controller Mode

see Figure 6-64

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SM4

tsu(POCI-SPICLK)

Setup time, SPIn_D[x] valid before SPIn_CLK active edge

2.8

SM5

th(SPICLK-POCI)

Hold time, SPIn_D[x] valid after SPIn_CLK active edge

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

PHA=1

EPOL=1

POL=0

POL=1

POL=0

POL=1

SM8

SM9

SM3

SM1

SM2

SM1

SM8

SM9

SM3

SM1

SM2

SM1

SM2

SM3

SM2

SM3

SM4

SM5

SM4

SM5

SM4

SM5

SPRSP08_TIMING_McSPI_02

Figure 6-64. SPI Controller Mode Receive Timing

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AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

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