AM67 datasheet(174/237 Pages) TI

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6.9.5.17.2 MCSPI — Peripheral Mode

Table 6-79, Figure 6-66, Table 6-80, and Figure 6-67 present timing requirements and switching characteristics

for SPI – Peripheral Mode.

Table 6-79. MCSPI Timing Requirements – Peripheral Mode

see Figure 6-66

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SS1

tc(SPICLK)

Cycle time, SPIn_CLK

SS2

tw(SPICLKL)

Pulse duration, SPIn_CLK low

0.45P

(1)

SS3

tw(SPICLKH)

Pulse duration, SPIn_CLK high

0.45P

(1)

SS4

tsu(PICO-SPICLK)

Setup time, SPIn_D[x] valid before SPIn_CLK active edge

SS5

th(SPICLK-PICO)

Hold time, SPIn_D[x] valid after SPIn_CLK active edge

SS8

tsu(CS-SPICLK)

Setup time, SPIn_CSi valid before SPIn_CLK first edge

SS9

th(SPICLK-CS)

Hold time, SPIn_CSi valid after SPIn_CLK last edge

(1)

P = SPIn_CLK period in ns.

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS8

SS9

SS8

SS9

SS2

SS3

SS2

SS4

SS5

SS4

SS5

SS4

SS5

SPRSP08_TIMING_McSPI_04

Figure 6-66. SPI Peripheral Mode Receive Timing

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

174

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