AM67 datasheet(187/237 Pages) TI

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6.9.5.18.1.8 UHS–I SDR50 Mode

Table 6-96 and Figure 6-81 presents switching characteristics for MMC0 – UHS-I SDR50 Mode.

Table 6-96. Switching Characteristics for MMC0 – UHS-I SDR50 Mode

see Figure 6-81

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

100

MHz

SDR505

tc(clk)

Cycle time, MMC0_CLK

SDR506

tw(clkH)

Pulse duration, MMC0_CLK high

4.45

SDR507

tw(clkL)

Pulse duration, MMC0_CLK low

4.45

SDR508

td(clkL-cmdV)

Delay time, MMC0_CLK rising edge to MMC0_CMD transition

1.2

6.35

SDR509

td(clkL-dV)

Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition

1.2

6.35

MMC[ ]_CLK

MMC

CMD

[ ]_

MMC

DAT

[x]_

[3:0]

SDR505

SDR507

SDR506

SDR508

SDR509

SDR508

SDR509

Figure 6-81. MMC0 – UHS-I SDR50 – Transmit Mode

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AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

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