AM67 datasheet(188/237 Pages) TI

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6.9.5.18.1.9 UHS–I DDR50 Mode

Table 6-97 and Figure 6-82 present switching characteristics for MMC0 – UHS-I DDR50 Mode.

Table 6-97. Switching Characteristics for MMC0 – UHS-I DDR50 Mode

see Figure 6-82

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

DDR505

tc(clk)

Cycle time, MMC0_CLK

DDR506

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

DDR507

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

DDR508

td(clk-cmdV)

Delay time, MMC0_CLK rising edge to MMC0_CMD transition

1.12

6.43

DDR509

td(clk-dV)

Delay time, MMC0_CLK transition to MMC0_DAT[3:0] transition

1.12

6.43

MMC[x] CLK

MMC[x] CMD

MMC[x] DAT3

[ :0]

DDR508

DDR509

DDR505

DDR506

DDR507

Figure 6-82. MMC0 – UHS-I DDR50 – Transmit Mode

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

188

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