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AD9245

Rev. D | Page 20 of 32

JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (fINPUT) due only to aperture jitter (tJ) can be

calculated with the following equation:

SNR = −20log10[2π fINPUT × tj]

In the equation, the rms aperture jitter represents the root-

mean square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter

(see Figure 43).

The clock input should be treated as an analog signal in cases

where aperture jitter can affect the dynamic range of the

AD9245. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the last step.

INPUT FREQUENCY (MHz)

1000

100

0.2ps

MEASURED SNR

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

Figure 43. SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 44, the power dissipated by the AD9245 is

proportional to its sample rate. The digital power dissipation is

determined primarily by the strength of the digital drivers and

the load on each output bit. The maximum DRVDD current

(IDRVDD) can be calculated as

CLK

LOAD

DRVDD

where N is the number of output bits, 14 in the case of the

AD9245. This maximum current occurs when every output bit

switches on every clock cycle, that is, a full-scale square wave at

the Nyquist frequency, fCLK/2. In practice, the DRVDD current

is established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal.

450

400

350

300

250

200

150

100

2030

4050

SAMPLE RATE (MSPS)

AD9245-80

AD9245-65

AD9245-40

AD9245-20

Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 44 was

taken with the same operating conditions as those reported in

the Typical Performance Characteristics section, and with a

5 pF load on each output driver.

By asserting the PDWN pin high, the AD9245 is placed in

standby mode. In this state, the ADC typically dissipates

1 mW if the CLK and analog inputs are static. During standby,

the output drivers are placed in a high impedance state.

Reasserting the PDWN pin low returns the AD9245 to its

normal operational mode.

Low power dissipation in standby mode is achieved by shutting

down the reference, reference buffer, and biasing networks. The

decoupling capacitors on REFT and REFB are discharged when

entering standby mode and then must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode, and shorter standby

cycles result in proportionally shorter wake-up times. With the

recommended 0.1 μF and 10 μF decoupling capacitors on REFT

and REFB, it takes approximately 1 second to fully discharge the

reference buffer decoupling capacitors and 7 ms to restore full

operation.

DIGITAL OUTPUTS

The AD9245 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies, which can affect converter performance.

Applications requiring the ADC to drive large capacitive loads or

large fanouts can require external buffers or latches.

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