AD9245 datasheet(21/32 Pages) AD

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AD9245

Rev. D | Page 21 of 32

As detailed in Table 11, the data format can be selected for either

offset binary or twos complement.

TIMING

The AD9245 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD9245. These transients can degrade the converter’s dynamic

performance.

The lowest typical conversion rate of the AD9245 is 1 MSPS. At

clock rates below 1 MSPS, dynamic performance can degrade.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9245. The input range can be adjusted by varying the

reference voltage applied to the AD9245 using either the

internal reference or an externally applied reference voltage.

The input span of the ADC tracks reference voltage changes

linearly. The various reference modes are summarized in Table 10

and described in the following sections.

If the ADC is being driven differentially through a transformer,

the reference voltage can be used to bias the center tap

(common-mode voltage).

INTERNAL REFERENCE CONNECTION

A comparator within the AD9245 detects the potential at the

SENSE pin and configures the reference into one of four

possible states, which are summarized in Table 10. If SENSE is

grounded, the reference amplifier switch is connected to the

internal resistor divider (see Figure 45), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected as shown in Figure 47, the switch is again set to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

⎟

⎠

⎞

⎜

⎝

⎛ +

VREF

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

μF

0.1

μF

VREF

SENSE

0.5V

AD9245

VIN–

VIN+

REFT

0.1

μF

0.1

μF

0.1

μF

REFB

SELECT

LOGIC

ADC

CORE

Figure 45. Internal Reference Configuration

If the internal reference of the AD9245 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 46 depicts

how the internal reference voltage is affected by loading. A

2 mA load is the maximum recommended load.

LOAD (mA)

0.05

0.5

1.0

1.5

2.0

2.5

3.0

–0.25

–0.20

–0.15

–0.10

–0.05

0.5V ERROR (%)

1.0V ERROR (%)

Figure 46. VREF Accuracy vs. Load

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

AVDD

N/A

2 × External Reference

Internal Fixed Reference

VREF

0.5

1.0

Programmable Reference

0.2 V to VREF

⎟

⎠

⎞

⎜

⎝

⎛ +

0.5

(See Figure 47)

2 × VREF

Internal Fixed Reference

AGND to 0.2 V

1.0

2.0

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