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HT16514 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc |
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HT16514 Datasheet(HTML) 17 Page - Holtek Semiconductor Inc |
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17 / 39 page ![]() Parallel Mode (i80) Note: The input signal rising time and falling time (tf,tr) is specified at 15ns or less. All timing is specified using 20% and 80% of VDD as the reference. tCCLW and tCCLR are specified as the overlap between CS as L and WR and RD at the L level. Timing Conditions 3 for Serial Mode Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions tCYK Shift Clock Cycle 4.5V~5.5V SCK 500 ¾¾ ns 2.7V~4.5V 1000 ¾¾ ns tWHK High-level Shift Clock Pulse Width 4.5V~5.5V SCK 200 ¾¾ ns 2.7V~4.5V 300 ¾¾ ns tWLK Low-level Shift Clock Pulse Width 4.5V~5.5V SCK 200 ¾¾ ns 2.7V~4.5V 300 ¾¾ ns tHSTBK Shift Clock Hold Time 4.5V~5.5V STD ¯® SCK¯ 100 ¾¾ ns 2.7V~4.5V 150 ¾¾ ns tDS Data Setup Time 4.5V~5.5V Data ® SCK 100 ¾¾ ns 2.7V~4.5V 150 ¾¾ ns tDK Data Hold Time 4.5V~5.5V SCK ® Data 100 ¾¾ ns 2.7V~4.5V 150 ¾¾ ns tDKSTB ST Hold Time 4.5V~5.5V SCK ® ST 500 ¾¾ ns 2.7V~4.5V 750 ¾¾ ns tWSTB ST Pulse Width 4.5V~5.5V ¾ 500 ¾¾ ns 2.7V~4.5V 750 ¾¾ ns tWAIT Wait Time 4.5V~5.5V 8th CLK ® 1st CLK¯ 1 ¾¾ ms 2.7V~4.5V 1 ¾¾ ms tODO Output Data Delay Time 4.5V~5.5V ST ¯® Data ¾¾ 150 ns 2.7V~4.5V ¾¾ 300 ns HT16514 Rev. 1.00 17 October 4, 2006 R S C S W R , R D D B 0 ~ D B 7 ( W r i t e ) D B 0 ~ D B 7 ( R e a d ) t f t r t R H 8 t C Y C 8 t R S 8 t C C L R , t C C L W t D S 8 t A C C 8 t O H 8 t D H 8 t C C H R , t C C H W t f |
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