Functional Description

CPU Interface

HT16514 have 4 or 8-bit parallel interface or serial interface. These modes are selected by IM pin.

²0²: Serial mode

²1²: Parallel mode

CPU Interface Table

IM

CS

RS, ST

E (RD), SCK

R, W (WR)

MPU

SI, SO

DB0~DB7

0CS

ST

SCK

Note

Note

SI, SO

Note

1CS

RS

E (RD)

R,W(WR)

MPU

Note

DB0~DB7

Note: Keep this pin Hi or Lo.

Registers (IR, DR)

The HT16514 has two 8-bit registers, namely, an instruction register (IR) and a data register (DR). The IR register

stores instruction code such as display clear and cursor shift. It also contains address information for display data RAM

(DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily

stores data to be written into or read from the DDRAM or CGRAM. Data written into the DR from the MPU is automati-

cally written into the DDRAM or CGRAM by internal operation. The DR is also used for data storage when reading data

from the DDRAM or CGRAM. When the address information is written into the IR, data is read and then stored into the

DR from the DDRAM or CGRAM by internal operation. Data transfer between the MPU is completed when the MPU

reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the

MPU. These two registers can be selected by the register selector (RS) signal, (Refer to CPU Interface table).

Registers (IR, DR) Table

Common

M68

i80

Register Selection

RS

R, W

RD

WR

0010

Write IR data during internal operation (display clear, etc.)

0101

Read data to be busy flag (DB7) and address counter (DB6~DB0)

1010

Write DR data (DR

®DDRAM, CGRAM)

1101

Read DR data (DDRAM, CGRAM

®DR)

Busy Flag (Read BF Flag)

Busy flag data (DB7) is always output as

²0².

Address Counter (AC)

The Address counter (AC) assigns address to both DDRAM and CGRAM. When an instruction address is written into

the IR, the address information is sent from the IR to the AC.

Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (or read

from) the DDRAM or CGRAM, the AC is automatically incremented by 1 (or decremented by 1). The cursor position are

then output to DB0~DB6 when RS=0 and R, W=1 (Refer to Registers (IR, DR) Table).

HT16514

Rev. 1.00

20

October 4, 2006