Parallel mode for i80 (IM=1, MPU=0)

When setting

²IM=1, MPU=0², i80 is selected. In the HT16514, each time data is sent from the MPU, a type of pipeline

process between LSIs is performed through the bus holder attached to internal data bus.

There is a certain restriction in the read sequence of this display data RAM. Please be advised that data of the specified

address is not generated by the read instruction issued immediately after the address setup. This data is generated in

data read for the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is

selected. This relationship is shown in the following figure.

HT16514

Rev. 1.00

28

October 4, 2006

W r i t i n g M P U

W R

D A T A

I n t e r n a l T i m i n g

B U S

H o l d e r

W r i t e

S i g n a l

L a t c h

N

N + 1

N + 2

N + 3

N

N + 1

N + 2

N + 3

R e a d i n g M P U

W R

D A T A

I n t e r n a l T i m i n g

A d d r e s s

P r e s e t

R e a d

S i g n a l

N

n

n + 1

N

R D

C o l u m n

A d d r e s s

B U S

H o l d e r

P r e s e t N

I n c r e m e n t N + 1

N + 2

N

n

n + 1

n + 2

A d d r e s s S e t

# n

D u m m y

R e a d

D a t a R e a d

# n

D a t a R e a d

# n + 1