TSC2006 datasheet(27/46 Pages) TI

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Configuration Register 1

TSC2006

SBAS415A – JUNE 2007 – REVISED NOVEMBER 2007

Table 18. Sense Time Selection

SNS2

SNS1

SNS0

SENSE TIME (tSNS)

µs

544

µs

608

µs

2.080ms

2.144ms

2.592ms

2.656ms

DTW—Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables pen touch detection in the

background while waiting for the host to issue the converter function in host-initiated/controlled modes. This

background detection allows the TSC2006 to pull high at PINTDAV to indicate no pen touch detected while

waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert

function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode

until the next pen touch is detected.

LSM—Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normal

sampling cycles of each conversion. This additional time is represented as approximately two internal oscillator

clock cycles. For SNSVDD = 1.2V at –40

°C, the LSM bit should be set to '1' so that the sampled signal has

enough time to settle.

Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection.

Table 19. Configuration Register 1 (Reset Value = 0000h)

MSB

LSB

D15

D14

D13

D12

D11

D10

Resrvd

TBM3

TBM2

TBM1

TBM0

Resrvd

BTD2

BTD1

BTD0

TBM3-TBM0—Connection test-bit modes (patent pending). These bits specify the mode of test bits used for the

predefined range of the combined X-axis and Y-axis touch screen panel resistance (RTS).

Table 20. Touch Screen Resistance Range and Test-Bit Modes

TEST-BIT MODES

RTS

TBM3

TBM2

TBM1

TBM0

Ω)

0.17

0.17 < RTS ≤ 0.52

0.52 < RTS ≤ 0.86

0.86 < RTS ≤ 1.6

1.6 < RTS ≤ 2.2

2.2 < RTS ≤ 3.6

3.6 < RTS ≤ 5.0

5.0 < RTS ≤ 7.8

7.8 < RTS ≤ 10.5

10.5 < RTS ≤ 16.0

16.0 < RTS ≤ 21.6

21.6 < RTS ≤ 32.6

Reserved

Only for short-circuit panel test

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