TSC2006 datasheet(30/46 Pages) TI

30 / 46 page

www.ti.com

Converter Function Select Register

TSC2006

SBAS415A – JUNE 2007 – REVISED NOVEMBER 2007

The Converter Function Select (CFN) register reflects the converter function select status.

Table 25. Converter Function Select Status Register (Reset Value = 0000h)

MSB

LSB

D15

D14

D13

D12

D11

D10

CFN15

CFN14

CFN13

CFN12

CFN11

CFN10

CFN9

CFN8

CFN7

CFN6

CFN5

CFN4

CFN3

CFN2

CFN1

CFN0

CFN15-CFN0—Converter function select status. These bits represent the converter function currently running,

which is set in bits C3-C0 of Control Byte 1. When the CFNx bit shows '1', where x is the decimal value of

converter function select bits C3-C0, it indicates that the converter function that is set in bits C3-C0 is running.

For example, when CFN2 shows '1', it indicates the converter function set in bits C3-C0 ('0010') is running. The

CFNx bits are reset to 0000h whenever the converter function is complete, stopped by STS bit, or reset (by the

hardware reset from the RESET pin or the software reset from SWRST bit in Control Byte 1). However, if the

TSC-initiated scan function mode is issued (by setting the PSM bit in the CFR0 register to '1'), the CFN0 or

CFN1 bit will not be reset when the corresponding converter function is complete because there is no pen touch.

This event allows the TSC2006 to immediately initiate the scan process (corresponding to CFN0 or CFN1 set to

'1') when the next pen touch is detected.

Table 26. STATUS Register (Reset Value = 0004h)

MSB

LSB

D15

D14

D13

D12

D11

D10

DAV

RESRVD

RESET

RESRVD

Due

PDST

ID1

ID0

(read '0')

Flag

CON

(read '0')

SHR

AUX

TEMP1

TEMP2

DAV Bits—Data available bits. These seven bits mirror the operation of the internal signals of DAV. When any

processed data are stored in data registers, the corresponding DAV bit is set to '1'. It stays at '1' until the

Table 27. DAV Function

DAV

DESCRIPTION

No new processed data are available.

Processed data are available. This bit stays at 1 until the host has read out all updated registers.

RESET Flag—See Table 28 for the interpretation of the RESET flag bits.

Table 28. RESET Flag Bits

RESET Flag

DESCRIPTION

Device was reset since last status poll (hardware or software reset).

Device has not been reset since last status poll.

X CON—This bit is '1' if the X axis of the touch screen panel is properly connected to the X drivers. This bit is the

connection test result.

Y CON—This bit is '1' if the Y axis of the touch screen panel is properly connected to the Y drivers. This bit is the

connection test result.

Y SHR—This bit is '1' if there is no short-circuit tested at the Y axis of the touch screen panel. This bit is the

short-circuit test result.

PDST—Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows '0',

it indicates A/D converter bias circuitry is still powered on after each conversion and before the next sampling;

otherwise, it indicates A/D converter bias circuitry is powered down after each conversion and before the next

sampling. However, it is powered down between conversion sets. Because this status bit is synchronized with

the internal clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converter

function is running.

ID[1:0] Device ID bits: These bits represent the version ID of TSC2006. This version defaults to '00'.

Submit Documentation Feedback

Product Folder Link(s): TSC2006

TSC2006 Datasheet(PDF) 30 Page - Texas Instruments

TSC2006 Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL