TMP89FS60 datasheet(311/410 Pages) TOSHIBA

311 / 410 page

Page 297

TMP89FS60

RA001

Note 1: A read of ADCDRL or ADCDRH must be read after the INTADC interrupt is generated or after ADCCR2<EOCF> becomes

"1".

Note 2: In single mode, do not read ADCDRL or ADCDRH during AD conversion (ADCCR2<ADBF>="1"). (If AD conversion is fin-

ished in the interim between a read of ADCDRL and a read of ADCDRH, the INTADC interrupt request is canceled, and

the conversion result is lost.)

Note 3: If STOP, IDLE0 or SLOW mode is started, ADCDRL and ADCDRH are initialized to "0".

Note 4: If ADCCR1<AMD> is set to "00", ADCDRL and ADCDRH are initialized to "0".

Note 5: If an instruction to read ADCDRH is executed, "0" is read from bits 7 through 2.

Note 6: If AD conversion is finished in repeat mode in the interim between a read of ADCDRL and a read of ADCDRH, the previ-

ous converted value is retained without overwriting the AD converted value register. In this case, the INTADC interrupt

request is canceled, and the conversion result is lost.

AD converted value register (lower side)

ADCDRL

76543

210

(0x0036)

Bit Symbol

AD07

AD06

AD05

AD04

AD03

AD02

AD01

AD00

Read/Write

RRRRRRRR

After reset

00000

000

AD converted value register (upper side)

ADCDRH

76543

210

(0x0037)

Bit Symbol

-----

AD09

AD08

Read/Write

RRRRRRRR

After reset

00000

000

TMP89FS60 Datasheet(PDF) 311 Page - Toshiba Semiconductor

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