TMP89FS60 datasheet(312/410 Pages) TOSHIBA

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20. 10-bit AD Converter (ADC)

20.3 Functions

TMP89FS60

RA001

20.3

Functions

The 10-bit AD converter operates in either single mode in which AD conversion is performed only once or repeat

mode in which AD conversion is performed repeatedly.

20.3.1 Single mode

In single mode, the voltage at a designated analog input pin is AD converted only once.

Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "01" allows AD conversion to start.

ADCCR1<ADRS> is automatically cleared after the start of AD conversion. As AD conversion starts,

ADCCR2<ADBF> is set to "1". It is cleared to "0" if AD conversion is finished or if AD conversion is forced

to stop.

After AD conversion is finished, the conversion result is stored in the AD converted value registers

(ADCDRL and ADCDRH), ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt

(INTADC) is generated. The AD converted value registers (ADCDRL and ADCDRH) should be usually read

according to the INTADC interrupt processing routine. If the upper side (ADCDRH) of the AD converted

value register is read, ADCCR2<EOCF> is cleared to "0".

Note:Do not perform the following operations on the ADCCR1 register when AD conversion is being executed

(ADCCR2<ADBF>="1"). If the following operations are performed, there is the possibility that AD conversion

may not be executed properly.

• Changing the ADCCR1<SAIN> setting

• Setting ADCCR1<AINEN> to "0"

• Changing the ADCCR1<AMD> setting (except a forced stop by setting AMD to "00")

• Setting ADCCR1<ADRS> to "1"

Figure 20-2 Single Mode

20.3.2 Repeat mode

In repeat mode, the voltage at an analog input pin designated at ADCCR1<SAIN> is AD converted repeat-

edly.

Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "11" allows AD conversion to start.

After the start of AD conversion, ADCCR1<ADRS> is automatically cleared. After the first AD conversion is

finished, the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH),

ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt (INTADC) is generated. After this

interrupt is generated, the second (next) AD conversion starts immediately.

Status of ADCDRL

and ADCDRH

Clearing EOCF based on

the conversion result

Read of conversion result

ADCCR2<EOCF>

INTADC interrupt

request

ADCCR2<ADBF>

ADCCR1<ADRS>

Result of the first conversion

Result of the second conversion

Indeterminate

AD conversion start

Read of ADCDRH

Read of ADCDRL

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