TMPR4951B datasheet(106/256 Pages) TOSHIBA

106 / 256 page

Chapter 5 Cache Organization

5-4

5.2.6

Organization of the Data Cache (D-Cache)

Each line of D-cache data has an associated 25-bit tag.

The TX4951B processor D-cache has the following characteristics:

•

Cache size: 8 KB

•

Four-way set associative

•

FIFO replacement

•

Indexed with a virtual address

•

Checked with a physical tag

•

Block (line) size: 8 words (32 bytes)

•

Burst size: 8 words (32 bytes)

•

Store buffer

•

Lockable on a per-line basis (way1

∼ way3)

•

Write-back or write-through on a per-page basis

•

All write-back, CS, FIFO and lock bits are cleared by a Reset exception

5.2.7

Data cache address field

Figure 5.2.5 shows the data cache address field.

Cache Tag Index

(6 bits)

Physical Tag

(25 bits )

Word

(2 bits)

Byte

(3 bits)

Figure 5.2.5 Data cache address field

5.2.8

Data cache configuration

Each line in the 4 ways of the data cache share F1, F0 replacement bits. Figure 5.2.6 shows the

format of replacement bits. These bits are shared by way0, way1, way2 and way3 for 8 KB cache, and

indicate next set to which replacement will be directed; when lock bit is set to 1, indicate this set is not

locked.

Each line of data cache data has an associated 29-bit tag that contains a 25-bit physical address, a

single Lock bit, a single write-back bit and a 2-bit cache state, except for the line in way0, which has an

28-bit tag that excludes a Lock bit. Figure 5.2.7 shows the formats of tag and data pair.

F0: FIFO replace bit 0

F1: FIFO replace bit 1

Figure 5.2.6 Format of replacement bits

TMPR4951B Datasheet(PDF) 106 Page - Toshiba Semiconductor

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