AM69 datasheet(146/326 Pages) TI1

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Table 5-121. Connectivity Requirements (continued)

ALY

BALL

NUMBER

AND

BALL

NUMBER

BALL NAME

CONNECTION REQUIREMENT

P36

E26

MCU_ADC0_AIN0

Each of these balls can be connected to VSS through a separate

external pull resistor or can be connected directly to VSS to ensure

these balls are held to a valid logic low-level, if unused.

V36

F25

MCU_ADC0_AIN1

T34

F23

MCU_ADC0_AIN2

T36

A28

MCU_ADC0_AIN3

P34

E24

MCU_ADC0_AIN4

R37

D27

MCU_ADC0_AIN5

R33

A26

MCU_ADC0_AIN6

V38

B27

MCU_ADC0_AIN7

Y38

C32

MCU_ADC1_AIN0

Y34

B33

MCU_ADC1_AIN1

V34

B31

MCU_ADC1_AIN2

W37

B29

MCU_ADC1_AIN3

AA37

D31

MCU_ADC1_AIN4

W33

A32

MCU_ADC1_AIN5

U33

A30

MCU_ADC1_AIN6

Y36

C28

MCU_ADC1_AIN7

AN11

AG7

SERDES0_REXT

Each of these balls must be connected to VSS through appropriate

external pull resistor to ensure these balls are held to a valid logic low

level, if unused. Refer to Signal Descriptions footnote for appropriate

value of pull-resistor for each signal.

AL9

AH9

SERDES1_REXT

AL20

SERDES2_REXT

AM19

AH23

SERDES4_REXT

AM28

AH31

CSI0_RXRCALIB

AL28

AJ33

CSI1_RXRCALIB

AM31

AH29

CSI2_RXRCALIB

AE8

DDR0_CAL0

G14

DDR1_CAL0

DDR2_CAL0

F18

DDR3_CAL0

AM24

AH25

DSI0_TXRCALIB

AL22

AH27

DSI1_TXRCALIB

AN18

AH22

USB0_RCALIB

AM69A, AM69

SPRSP92D – FEBRUARY 2023 – REVISED DECEMBER 2024

www.ti.com

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