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(2)

All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.

(3)

VDD_* includes: VDD_CORE, VDD_CPU, VDD_MCU, VDD_MCU_WAKE1, VDD_WAKE0

VDDAR_* includes: VDDAR_CORE, VDDAR_CPU, VDDAR_MCU

VDDA_0P8_* includes: VDDA_0P8_CSIRX0_1, VDDA_0P8_CSIRX2, VDDA_0P8_DLL_MMC0, VDDA_0P8_DSITX,

VDDA_0P8_DSITX_C, VDDA_0P8_PLL_DDR0, VDDA_0P8_PLL_DDR1, VDDA_0P8_PLL_DDR2, VDDA_0P8_PLL_DDR3,

VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2, VDDA_0P8_SERDES_C4, VDDA_0P8_SERDES0_1,

VDDA_0P8_SERDES2, VDDA_0P8_SERDES4, VDDA_0P8_UFS, VDDA_0P8_USB

VDDA_1P8_* includes: VDDA_1P8_CSIRX0_1, VDDA_1P8_CSIRX2, VDDA_1P8_DSITX, VDDA_1P8_SERDES0_1,

VDDA_1P8_SERDES2, VDDA_1P8_SERDES2_4, VDDA_1P8_SERDES4, VDDA_1P8_UFS, VDDA_1P8_USB

VDDA_* includes: VDDA_ADC0, VDDA_ADC1, VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_OSC1, VDDA_PLLGRP0,

VDDA_PLLGRP1, VDDA_PLLGRP10, VDDA_PLLGRP12, VDDA_PLLGRP13, VDDA_PLLGRP2, VDDA_PLLGRP5,

VDDA_PLLGRP6, VDDA_PLLGRP7, VDDA_PLLGRP8, VDDA_PLLGRP9, VDDA_POR_WKUP, VDDA_TEMP0, VDDA_TEMP1,

VDDA_TEMP2, VDDA_TEMP3, VDDA_TEMP4, VDDA_WKUP

VDDS_DDR_* includes: VDDS_DDR, VDDS_DDR_C0, VDDS_DDR_C1, VDDS_DDR_C2, VDDS_DDR_C3

VDDSHV* includes: VDDSHV0, VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2, VDDSHV2_MCU, VDDSHV5

(4)

This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For

example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be

–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used

to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,

including power supply ramp–up and ramp–down sequences.

(5)

For current pulse injection:

Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times

maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.

For overvoltage performance:

Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.

(6)

For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning

to ambient room temperature before usage.

(7)

VDD is the voltage on the corresponding power-supply pin(s) for the IO.

(8)

The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply

Monitor Design Guidelines using VMON/POK.

(9)

An external resistor divider is required to limit the voltage applied to this device pin. For more information, see the USB VBUS Design

Guidelines.

Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply

voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO

power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, and NMIn

are the only fail–safe IO terminals. All other IO terminals are not fail–safe and the voltage applied to them should

be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Absolute Maximum

Ratings.

overshoot

undershoot

period

Overshoot = 20% of nominal

IO supply voltage

Undershoot = 20% of nominal

IO supply voltage

Tovershoot + Tundershoot < 20% of Tperiod

Figure 6-1. IO Transient Voltage Ranges

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

±1000

Charged-device model (CDM), per AEC Q100-011

All pins

±250

Corner pins (A1,

AJ29)

±750

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

AM69A, AM69

SPRSP92D – FEBRUARY 2023 – REVISED DECEMBER 2024

www.ti.com

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