TMP88CS38 datasheet(175/226 Pages) TOSHIBA

175 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-175

(2) Interrupt generator circuit

An interrupt request is generated when a falling edge of VD signal or when line

counter (DCTR) is counted to the certain value specified by ISDC.

Interrupt source select register (1 bit) ..... SVD (Bit4 in ORIRC)

“0”

......... Interrupt request generated when the display line counter

(DCTR) is counted to the certain value which is specified by

ISDC.

“1”

......... Interrupt request is generated when a falling edge of VD

signal.

Interrupt generation line specification register (4 bits) ...... ISDC (Bit3 to 0 in

ORIRC)

“0000”

......... Interrupt request generated when the display line counter

is cleared.

“0001”

......... Interrupt request generated at end points of the last

scanning line of the first display line

“0010”

......... Interrupt request generated at end points of the last

scanning line of the 2’nd display line

“1111”

......... Interrupt request generated at end points of the last

scanning line of the 15’th display line

2.15.5.7 Display Memory Access

(1) Display memory

The display memory is accessed for two purposes, one for writing data to the

display memory, and one for reading data from the display memory.

Display memory address specification registers

(9 bits)

.... DMA8 to MDA0 (ORDMA)

Display memory data write registers

Character code write register (9 bits)

.... CRA8 to CRA0 (ORCRA)

Character ornamentation data write registers

(7 bits)

.... SLNT, EUL, BLF, IDT, RDT,

GDT, and BDT (ORDSN)

Display memory bank select register MBK (Bit1 in ORETC)

“0”

......... When writing either character code or character ornamentation data

“1”

......... When writing both character code and character ornamentation data

Note 1: These control registers have a characteristic that immediately when a value is

written to the register, the content of the register is transferred as valid data to the

OSD circuit/display memory.

Note 2: The data written to the display memory takes effect at the same time it is written. When

character code or character ornamentation data is written to the display memory while

it is displaying some character, the character may not be displayed correctly. When

writing data to the display memory, make sure no character is being displayed in the

memory location where you are going to write data.

Note 3: When writing data to or reading data from the display memory, do not use two-byte

transfer instructions such as “LDW(HL),mn LD rr, (pp)”. Otherwise, erroneous data

may be written to the display memory or data may be written to an incorrect

address.

Note 4: Allow for at least two instruction cycles between a display memory address write

instruction and a data write or read instruction. Also, when continuous writing data

to or reading data from the display memory, allow for at least two instruction cycles

between one write or read instruction and the next. Otherwise, erroneous data

may be written to the display memory or data may be written to an incorrect

address.

Note 5: When setting display memory addresses, always be sure to write all of 9 address

bits sequentially in order of DMA8 and DMA7 to DMA0.

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