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33879 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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33879 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 26 page ![]() NXP Semiconductors 11 33879 4.4 Timing diagrams Figure 4. SPI timing diagram Figure 5. Valid data delay time and valid time test circuit Figure 6. Valid data delay time and valid time waveforms tDO(DIS) 0.7 VDD 0.2 VDD 0.2 VDD 0.7 VDD 0.2 VDD tLEAD tDO(EN) tDI(SU) tDI(HOLD) tVALID tLAG CS SCLK DI DO MSB in MSB out LSB out 0.7 VDD 0.2 VDD DO CL = 200 pF VDD = 5.0 V SCLK 33879 Under Test NOTE: CL represents the total capacitance of the test fixture and probe. (Low-to-High) tF(DI tR(DI) 0.2 VDD 0.7 VDD 0.2 0.7 VDD tVALID tR(DO VOL VOH VOL VOH 0.2 VDD 0.7 VDD 0 V 3.3/5.0 V < 50 ns 50% < 50 ns DO SCLK (High-to-Low) DO |
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