NXP Semiconductors

17

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Figure 15. SPI interface with microcontroller

All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. When a SPI bit is programmed to a

logic [0], the corresponding output is OFF. Conversely, when a SPI bit is programmed to logic [1] the output being controlled is ON.

Diagnostics are treated in a similar manner. Outputs with a fault feed back (via DO) a logic [1] to the microcontroller, while normal

operating outputs provide a logic [0].

Figure 16 illustrates the daisy chain configuration using the 33879. Data from the MCU is clocked daisy chain through each device while

the CS bit is commanded low by the MCU. During each clock cycle, output status from the daisy chain is transferred to the MCU via the

Master In Slave Out (MISO) line. On rising edge of CS, command data stored in the input register is then transferred to the output driver.

Figure 16. 33879 SPI system daisy chain

Multiple 33879 devices can be controlled in a parallel input fashion using the SPI. Figure 17 illustrates the control of 24 loads using three

dedicated parallel MCU ports for chip select.

Receive

Buffer

Parallel

Ports

To

Logic

33879

MC68HCxx

Microcontroller

DO

DI

CS

SCLK

MISO

MOSI

Shift Register

Shift Register

16 Bits

16 Bits

MC68HCxx

Microcontroller

with

SPI Interface

8 Outputs

8 Outputs

8 Outputs

CS

MISO

MOSI

Parallel Port

SCLK

DO

DI

DO

DI

DO

DI

CS

CS

SCLK

SCLK

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