34704 datasheet(31/54 Pages) FREESCALE

31 / 54 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

34704

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

processor decision to either shutoff or not, in the mean time

the control loop will try to fix itself.

To avoid erroneous conditions, a 20 μs filter will be

implemented.

The OV/UV fault flag is masked during DVS until

DVSSTAT flag is asserted “Done”.

To keep the RST output low during ramp up and until the

soft start is done, the OV/UV protection is masked from

reporting that the output is in regulation.

LOGIC COMMANDS AND REGISTERS

I2C USER INTERFACE

The 34704 communicates via I2C using a default device

address $54 to access all user registers and program all

regulators features independently. Physical address is in a 7-

bit format. The extra bit to complete the 8-bit indicates the

reading or writing mode as shown in Figure 7 and Figure 8.

After each byte read or sent, the MC34704 answers with an

Acknowledge bit, indicating the bite was transferred

successfully.

Figure 7. Writing sequence I2C bit stream

Figure 8. Reading sequence I2C bit stream

USER PROGRAMMABLE REGISTERS

GrpC/E power sequencing setting (34704A Only)

The microprocessor can choose one of several voltage

sequence options for the GrpC/E supply (REG5), high

voltage supply (REG6), and negative voltage supply (REG7).

For 3 of the sequencing options, REG5 supply is controlled

and tied with REG6 and REG7 in a preset power sequence.

By default, only REG6 and REG7 are involved in the power

sequence and REG5 is independently controlled with GrpE.

34704A assigns 2 bits to program the GrpC/E power

sequencing options (CCDSEQ[1:0]). These bits value is

latched in at GrpC power up and will not be allowed to change

unless a power recycle happens.

ACK

0XXXXXXX

Sub-Address

(MSB=0)

XXXXXXXX

1010100 + 0

ACK

Data

ACK

7 bit Physical Address +

(w) bit

ACK

0XXXXXXX

Sub-Address

(MSB=0)

XXXXXXXX

1010100 + 0

ACK

Data

ACK

7 bit Physical Address +

(w) bit

Start Bit

End Bit

1 0 1 0 1

0 0 0

0 0 0 0 0 0 1 0

0 0 0 0 1 1 1 1

ACK

7 bit Physical ADD +

(w) bit

Sub-address

(MSB=1)

ACK

Physical

ADD + (r) bit

Data Read

1010100 + 0

1XXXXXXX

1010100 + 1

XXXXXXX

1 0 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 1 0 0

0 0 0 1 1 1 1 1

Start Bit

ACK

ACK End Bit

OPTION

MSB

LSB

GRPC/E ENABLED

GRPC/E DISABLED

(Default)

REG5 is independently controlled

REG6 and REG7 ramp up together.

REG5 is independently controlled

REG6 and REG7 ramp down together

34704 Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc

34704 Datasheet(HTML) 31 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL