SYNC

10k

S

R

Q

Q

DEADTIME

ONE-SHOT

5V

2.5V

I = f(RT)

LM5576Q0

SNOSB24B – OCTOBER 2008 – REVISED APRIL 2013

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Multiple LM5576Q0 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration all of the devices will be synchronized to the highest frequency device. The diagram in Figure 13

illustrates the SYNC input/output features of the LM5576Q0. The internal oscillator circuit drives the SYNC pin

with a strong pull-down / weak pull-up inverter. When the SYNC pin is pulled low either by the internal oscillator

or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the

SYNC pins of several LM5576Q0 IC’s are connected together, the IC with the highest internal clock frequency

will pull the connected SYNC pins low first and terminate the oscillator ramp cycles of the other IC’s. The

LM5576Q0 with the highest programmed clock frequency will serve as the master and control the switching

frequency of the all the devices with lower oscillator frequency.

Figure 13. Simplified Oscillator Block Diagram and SYNC I/O Circuit

ERROR AMPLIFIER AND PWM COMPARATOR

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.225V). The output of the error amplifier is

connected to the COMP pin allowing the user to provide loop compensation components, generally a type II

network, as illustrated in Figure 9. This network creates a pole at DC, a zero and a noise reducing high

frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to

the error amplifier output voltage at the COMP pin.

RAMP GENERATOR

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.

Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and

provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.

Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and

propagation delay limit the minimum achievable pulsewidth. In applications where the input voltage may be

relatively large in comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for

regulation. The LM5576Q0 utilizes a unique ramp generator, which does not actually measure the buck switch

current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp

signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The

current reconstruction is comprised of two elements; a sample & hold DC level and an emulated current ramp.

10

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